Datasheet

9. Interrupt
page 68
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0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
Figure 9.3.2. IFSR Register and IFSR2A Register
Interrupt request cause select register
Bit name Function
Bit symbol
RW
Symbol Address After reset
IFSR 035F
16 00 16
IFSR0
b7 b6 b5 b4 b3 b2 b1 b0
INT0 interrupt polarity
switching bit
0 : Reserved
1 : INT4
0 : Reserved
1 : INT5
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
INT1 interrupt polarity
switching bit
INT2 interrupt polarity
switching bit
INT3 interrupt polarity
switching bit
INT4 interrupt polarity
switching bit
INT5 interrupt polarity
switching bit
0 : One edge
1 : Both edges
Interrupt request cause
select bit
Interrupt request cause
select bit
IFSR1
IFSR2
IFSR3
IFSR4
IFSR5
IFSR6
IFSR7
RW
RW
RW
RW
RW
RW
RW
RW
(1)
(1)
(1)
(1)
(1)
(1)
NOTE:
1. When setting this bit to “1” (= both edges), make sure the POL bit in the INT0IC to INT5IC register is set to
“0” (= falling edge).
Interrupt request cause select register 2
Bit name Function
Bit symbol
RW
Symbol Address After reset
IFSR2A 035E
16 XXXXXXX0 2
b7 b6 b5 b4 b3 b2 b1 b0
Must be set to “1”.
(b7-b1)
Nothing is assigned. When write, set to “0”.
When read, their contents are indeterminate.
IFSR20
1
Reserved bit
RW
(1)
NOTE:
1. Set this bit to "1" before you enable interrupt after resetting.