Datasheet

9. Interrupt
page 67
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Figure 9.3.1. Interrupt Control Registers
Symbol Address After reset
INT3IC 0044
16 XX00X0002
INT5IC 004816 XX00X0002
INT4IC 004916 XX00X0002
INT0IC to INT2IC 005D16 to 005F16 XX00X0002
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
ILVL0
IR
PO
L
No functions are assigned.
When writing to these bits, write “0”. The values in these bits
when read are indeterminate.
Interrupt priority level
select bit
Interrupt request bit
Polarity select bit
Reserved bit
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge
(3)
1 : Selects rising edge
Must always be set to “0”
ILVL1
ILVL2
(1)
Interrupt control register
(2)
b7 b6 b5 b4 b3 b2 b1 b0
Bit name FunctionBit symbol
RW
Symbol Address After reset
BCNIC 004A
16 XXXXX0002
DM0IC, DM1IC 004B16, 004C16 XXXXX0002
KUPIC 004D16 XXXXX0002
ADIC 004E16 XXXXX0002
S0TIC to S2TIC 005116, 005316, 004F16 XXXXX0002
S0RIC to S2RIC 005216, 005416, 005016 XXXXX0002
TA0IC to TA4IC 005516 to 005916 XXXXX0002
TB0IC to TB2IC 005A16 to 005C16 XXXXX0002
ILVL0
IR
Interrupt priority level
select bit
Interrupt request bit
0 : Interrupt not requested
1 : Interrupt requested
ILVL1
ILVL2
No functions are assigned.
When writing to these bits, write “0”. The values in these bits
when read are indeterminate.
(1)
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0
RW
RW
RW
RW
(b7-b4)
RW
RW
RW
RW
RW
RW
RW
RW
(b7-b6)
(b5)
NOTES:
1.This bit can only be reset by writing “0” (Do not write “1”).
2. To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that
register. For details, see 19.5 Interrupts.
NOTES:
1. This bit can only be reset by writing “0” (Do not write “1”).
2. To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register.
For details, see 19.5 Interrupts.
3. If the IFSRi bit (i = 0 to 5) in the IFSR register is “1” (both edges), set the POL bit in the INTiIC register to “0” (falling
edge).
BCNIC, DM0IC, DM1IC, KUPIC, ADIC, S0TIC to S2TIC, S0RIC to S2RIC, TA0IC to TA4IC, TB0IC TO
TB2IC, INT3IC, INT4IC, INT5IC, INT0IC to INT2IC