Datasheet

9. Interrupt
page 64
923fo7002,51.beF00.2.veR
0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
Interrupt source Vector table addresses Remarks Reference
Address (L) to address (H)
Undefined instruction FFFDC16 to FFFDF16 Interrupt on UND instruction M16C/60, M16C/20
Overflow FFFE016 to FFFE316 Interrupt on INTO instruction serise software
BRK instruction FFFE416 to FFFE716 maual
Address match FFFE816 to FFFEB16 Address match interrupt
Single step (1) FFFEC16 to FFFEF16
Watchdog timer FFFF016 to FFFF316 Watchdog timer
Oscillation stop and
re-oscillation detection Clock generating circuit
Voltage down
detection Voltage detection circuit
________
DBC (1) FFFF416 to FFFF716
_______
NMI FFFF816 to FFFFB16
_______
NMI interrupt
Reset (2) FFFFC16 to FFFFF16 Reset
Figure 9.2.1. Interrupt Vector
Mid address
Low address
0 0 0 0 High address
0 0 0 0 0 0 0 0
Vector address (L)
LSB
MSB
Vector address (H)
9.2 Interrupts and Interrupt Vector
One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective
interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the
corresponding interrupt vector. Figure 9.2.1 shows the interrupt vector.
Table 9.2.1.1. Fixed Vector Tables
If the contents of address
FFFE716 is FF16, program ex-
ecution starts from the address
shown by the vector in the
relocatable vector table.
9.2.1 Fixed Vector Tables
The fixed vector tables are allocated to the addresses from FFFDC16 to FFFFF16. Table 9.2.1.1 lists the
fixed vector tables. In the flash memory version of microcomputer, the vector addresses (H) of fixed
vectors are used by the ID code check function. For details, refer to the section 17.3 Flash Memory
Rewrite Disabling Function.
NOTES:
1. Do not normally use this interrupt because it is provided exclusively for use by development tools.
2. The b3 to b0 in address 0FFFFF16 are reserve bits. Set these bits to “11112”.