Datasheet

7. Clock Generation Circuit
page 48
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0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
Figure 7.4.1. Procedure to Use PLL Clock as CPU Clock Source
START
Set the CM07 bit to “0” (main clock), the CM17 to CM16
bits to “00
2 ”(main clock undivided), and the CM06 bit to “0”
(CM16 and CM17 bits enabled).
(1)
Set the PLC02 to PLC00 bits (multiplying factor).
(To select a 16 MHz < PLL clock)
Set the PM20 bit to “0” (2-wait states).
Set the PLC07 bit to “1” (PLL operation).
Wait until the PLL clock becomes stable (t su (PLL)).
Set the CM11 bit to “1” (PLL clock for the CPU clock source).
END
NOTE:
1. PLL operation mode can be entered from high speed mode.