Datasheet

7. Clock Generation Circuit
page 44
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0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
Figure 7.7. PLC0 Register
PLC00
PLC01
PLC02
PLC07
(3)
(4)
Function
PLL control register 0 (1, 2)
PLL multiplying factor
select bit
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Reserved bit
Operation enable bit
0 0 0:
0 0 1: Multiply by 2
0 1 0: Multiply by 4
0 1 1:
1 0 0:
1 0 1:
1 1 0:
1 1 1:
0: PLL Off
1: PLL On
Must set to "1"
Bit name
Bit
symbol
Symbol Address After reset
PLC0 001C
16 0001 X010 2
RW
b1b0b2
Reserved bit Must set to "0"
Do not set
RW
RW
RW
RW
RW
RW
Do not set
(b4)
(b6-b5)
(b3)
b7 b6 b5 b4 b3 b2 b1 b0
0 10
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
2. When the PM21 bit in the PM2 register is "1" (clock modification disable), writing to this register has
no effect.
3.
These three bits can only be modified when the PLC07 bit is set to "0" (PLL turned off). The value once
written to this bit cannot be modified.
4. Before setting this bit to "1" , set the CM07 bit to "0" (main clock), set the CM17 and CM16 bits to
"00
2 " (main clock undivided mode), and set the CM06 bit to "0" (CM16 and CM17 bits enable).