Datasheet

7. Clock Generation Circuit
page 39
923fo7002,51.beF00.2.veR
0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
f
C3
2
CM00, CM01, CM02, CM04, CM05, CM06, CM07: CM0 register bits
CM10, CM11, CM16, CM17: CM1 register bits
PCLK0, PCLK1, PCLK5: PCLKR register bits
CM21, CM27 : CM2 register bits
1/32
Main clock
generating circuit
f
C
CM02
CM04
CM10=1(stop mode)
Q
S
R
WAIT instruction
CM05
QS
R
NMI
Interrupt request level judgment output
RESET
Software reset
f
C
CPU clock
CM07 = 0
CM07 = 1
a
d
1/2 1/2 1/2 1/2
CM06=0
CM17-CM16=00
2
CM06=0
CM17-CM16=01
2
CM06=0
CM17-CM16=10
2
CM06=1
CM06=0
CM17-CM16=11
2
d
a
Details of divider
Sub-clock
generating circuit
X
CIN X COUT
X OUT X IN
f
8
f
32
c
b
b
1/2
c
f 32SIO
f
8S
I
O
f AD
f
1
e
e
1/2 1/4 1/8 1/16
1/32
P
C
LK
0
=
1
PLL
frequency
s
y
nt
h
es
i
z
e
r
0
1
C
M21=
1
C
M11
C
M21=
0
PL
L
cloc
k
Sub-clock
O
n-chi
p
oscillato
r
cloc
k
P
C
LK
0
=
0
f
2
f
1
S
I
O
P
C
LK1=1
P
C
LK1=
0
f
2
S
I
O
Main
clock
Oscillation
stop, re-
oscillation
detection
circuit
D4INT clock
CLK OUT
I/O ports
PCLK5=0,CM01-CM00=00
2
PCLK5=0,CM01-CM00=01 2
PCLK5=1,
CM01-CM00=00
2
PCLK5=0,
CM01-CM00=10
2
PCLK5=0,
CM01-CM00=11
2
CM21
BCLK
Figure 7.1. Clock Generation Circuit
Phase
comparator
Charge
pump
Voltage
control
oscillator
(VCO)
PLL clock
Main clock
1/2
Programmable
counter
Internal low-
pass filter
PLL frequency synthesizer
Pulse generation
circuit for clock
edge detection
and charge,
discharge control
Charge,
discharge
circuit
Reset
generating
circuit
Oscillation stop,
re-oscillation
detection interrupt
generating circuit
Main
clock
Oscillation stop
detection reset
CM27=0
CM21 switch signal
Oscillation stop,
re-oscillation
detection signal
Oscillation stop, re-oscillation detection circuit
CM27=1
1/2 1/2 1/2
ROCR3-ROCR2=11 2
On-chip
oscillator
clock
1/8
1/4
1/2
ROCR3-ROCR2=10 2
ROCR3-ROCR2=01 2
ROCR1-ROCR0=00 2
f 1(ROC)
f 2(ROC)
f 3(ROC)
ROCR1-ROCR0=01 2
ROCR1-ROCR0=11 2
On-chip Oscillator