Datasheet

6. Processor Mode
page 36
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0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
Figure 6.2 PM2 Register
Function
Bit Symbol
Bit Name
Processeor Mode Register 2
(1)
Symbol Address After Reset
PM2 001E
16 XXX000002
RW
b7 b6 b5 b4 b3 b2 b1 b0
PM20
0
PM21
System clock protective bit
(3,4)
RW
RW
RW
(b7-b5)
PM22
PM24
(b3)
Reserved bit Set to “0” RW
RW
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to “1” (write enable).
2. The PM20 bit become effective when PLC07 bit in the PLC0 register is set to "1" (PLL on). Change the PM20 bit
when the PLC07 bit is set to "0" (PLL off). Set the PM20 bit to "0" (2 waits) when PLL clock > 16 MHz.
3. Once this bit is set to “1”, it cannot be set to “0” by program.
4. Writing to the following bits has no effect when the PM21 bit is set to “1”:
CM02 bit in the CM0 register
CM05 bit in the CM0 register (main clock is not halted)
CM07 bit in the CM0 register (CPU clock source does not change)
CM10 bit in the CM1 register (stop mode is not entered)
CM11 bit in the CM1 register (CPU clock source does not change)
CM20 bit in the CM2 register (oscillation stop, re-oscillation detection function settings do not change)
All bits in the PLC0 register (PLL frequency synthesizer setting do not change)
When the PM21 bit is set to "1", do not execute the WAIT instruction.
5. Setting the PM22 bit to “1” results in the following conditions:
- The on-chip oscillator continues oscillating even if the CM21 bit in the CM2 register is set to "0" (main clock or
PLL clock) (system clock of count source selected by the CM21 bit is valid)
- The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer count
source.
- The CM10 bit in the CM1 register is disabled against write. (Writing a “1” has no effect, nor is stop mode
entered)
- The watchdog timer does not stop in wait mode.
6. For NMI function, the PM24 bit must be set to “1”(NMI function). Once this bit is set to “1”, it cannot be cleared to
“0” by program.
7. SD input is valid regardless of the PM24 setting.
Specifying wait when
accessing SFR during PLL
operation
(2)
0: 2 wait
1: 1 wait
WDT count source
protective bit
(3,5)
P85/NMI configuration bit
(6,7)
0: P8 5 function (NMI disable)
1: NMI function
0: CPU clock is used for the
watchdog timer count source
1: On-chip oscillator clock is used
for the watchdog timer count
source
0: Clock is protected by PRCR
register
1: Clock modification disabled
Nothing is assigned. When write, set to“0”.
When read,its content is indeterminate