Datasheet
Table Of Contents
- Notes regarding these materials
- General Precautions in the Handling of MPU/MCU Products
- How to Use This Manual
- Table of Contents
- Quick Reference by Address B-
- 1. Overview
- 2. Central Processing Unit (CPU)
- 2.1 Data Registers (R0, R1, R2 and R3)
- 2.2 Address Registers (A0 and A1)
- 2.3 Frame Base Register (FB)
- 2.4 Interrupt Table Register (INTB)
- 2.5 Program Counter (PC)
- 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
- 2.7 Static Base Register (SB)
- 2.8 Flag Register (FLG)
- 2.8.1 Carry Flag (C Flag)
- 2.8.2 Debug Flag (D Flag)
- 2.8.3 Zero Flag (Z Flag)
- 2.8.4 Sign Flag (S Flag)
- 2.8.5 Register Bank Select Flag (B Flag)
- 2.8.6 Overflow Flag (O Flag)
- 2.8.7 Interrupt Enable Flag (I Flag)
- 2.8.8 Stack Pointer Select Flag (U Flag)
- 2.8.9 Processor Interrupt Priority Level (IPL)
- 2.8.10 Reserved Area
- 3. Memory
- 4. Special Function Registers (SFRs)
- 5. Reset
- 6. Processor Mode
- 7. Clock Generation Circuit
- 8. Protection
- 9. Interrupt
- 10. Watchdog Timer
- 11. DMAC
- 12. Timer
- 13. Serial I/O
- 14. A/D Converter
- 15. CRC Calculation Circuit
- 16. Programmable I/O Ports
- 16.1 Port Pi Direction Register (PDi Register, i = 1, 6 to 10)
- 16.2 Port Pi Register (Pi Register, i = 1, 6 to 10)
- 16.3 Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers)
- 16.4 Port Control Register
- 16.5 Pin Assignment Control register (PACR)
- 16.6 Digital Debounce function
- 17. Flash Memory Version
- 17.1 Flash Memory Performance
- 17.2 Memory Map
- 17.3 Functions To Prevent Flash Memory from Rewriting
- 17.4 CPU Rewrite Mode
- 17.5 Register Description
- 17.6 Precautions in CPU Rewrite Mode
- 17.6.1 Operation Speed
- 17.6.2 Prohibited Instructions
- 17.6.3 Interrupts
- 17.6.4 How to Access
- 17.6.5 Writing in the User ROM Space
- 17.6.6 DMA Transfer
- 17.6.7 Writing Command and Data
- 17.6.8 Wait Mode
- 17.6.9 Stop Mode
- 17.6.10 Low Power Consumption Mode and On-chip Oscillator-Low Power Consumption Mode
- 17.7 Software Commands
- 17.8 Status Register
- 17.9 Standard Serial I/O Mode
- 17.10 Parallel I/O Mode
- 18. Electrical Characteristics
- 19. Usage Notes
- 19.1 SFR
- 19.2 PLL Frequency Synthesizer
- 19.3 Power Control
- 19.4 Protect
- 19.5 Interrupts
- 19.6 DMAC
- 19.7 Timer
- 19.8 Serial I/O
- 19.9 A/D Converter
- 19.10 Programmable I/O Ports
- 19.11 Electric Characteristic Differences Between Mask ROM
- 19.12 Mask ROM Version
- 19.13 Flash Memory Version
- 19.13.1 Functions to Inhibit Rewriting Flash Memory
- 19.13.2 Stop mode
- 19.13.3 Wait mode
- 19.13.4 Low power dissipation mode, on-chip oscillator low power dissipation mode
- 19.13.5 Writing command and data
- 19.13.6 Program Command
- 19.13.7 Operation speed
- 19.13.8 Instructions prohibited in EW0 Mode
- 19.13.9 Interrupts
- 19.13.10 How to access
- 19.13.11 Writing in the user ROM area
- 19.13.12 DMA transfer
- 19.13.13 Regarding Programming/Erasure Times and Execution Time
- 19.13.14 Definition of Programming/Erasure Times
- 19.13.15 Flash Memory Version Electrical Characteristics 10,000 E/W cycle product
- 19.13.16 Boot Mode
- 19.14 Noise
- 19.15 Instruction for a Device Use
- Appendix 1. Package Dimensions
- Appendix 2. Functional Difference
- Register Index
- REVISION HISTORY
5. Reset
page 30
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0020-2020B90JER
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Figure 5.5.2. VCR1 Register, VCR2 Register, and D4INT Register
VC13
V
o
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t
a
g
e
d
e
t
e
c
t
i
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n
r
e
g
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1
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d
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s
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f
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e
r
r
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e
t
(
2)
V
C
R
10
0
1
9
1
6
0
0
0
0
1
0
0
0
2
V
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a
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d
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f
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(1)
Bit name F unction
B
i
t
s
y
m
b
o
l
RW
b7 b6 b
5b
4b
3b
2b
1b
0
0:V
CC
< Vdet4
1:V
CC
≥ Vdet4
RO
0000 000
RW
RW
R
e
s
e
r
v
e
d
b
i
t
R
e
s
e
r
v
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d
b
i
t
M
u
s
t
se
t
t
o
“
0
”
M
u
s
t
s
e
t
t
o
“
0
”
V
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d
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c
t
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r
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g
i
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r
2
(1)
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m
b
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d
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s
sA
f
t
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r
r
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s
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t
(5)
V
C
R
20
0
1
A
1
6
0
0
1
6
B
i
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n
a
m
e
B
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t
s
y
m
b
o
l
b7 b6 b
5b
4b
3b
2b
1b
0
V
C
2
6
VC27
RW
RW
RW
RW
00000
F
u
n
c
t
i
o
n
Reserved bit Must set to “0”
Reset level monitor bit
(2, 3, 6)
0
:
D
i
s
a
b
l
e
r
e
s
e
t
l
e
v
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l
d
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t
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c
t
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n
c
i
r
c
u
i
t
1
:
E
n
a
b
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e
r
e
s
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t
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v
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l
d
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t
e
c
t
i
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n
c
i
r
c
u
i
t
Voltage down monitor
bit (4, 6)
0: Disable voltage down
detection circuit
1: Enable voltage down
detection circuit
(
b
2
-
b
0
)
(
b
7
-
b
4
)
(
b
5
-
b
0
)
0
NOTES:
1. The VC13 bit is useful when the VC27 bit in the VCR2 register is set to "1" (voltage down detection circuit
enable). The VC13 bit is always "1" (VCC ≥ Vdet4) when the VC27 bit in the VCR2 register is set to "0"
(voltage down detection circuit disable).
2. This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
NOTES:
1. Write to this register after setting the PRC3 bit in the PRCR register to “1” (write enable).
2. When not in stop mode, to use hardware reset 2, set the VC26 bit to “1” (reset level detection circuit enable).
3. VC26 bit is disabled in stop mode. (The microcomputer is not reset even if the voltage input to Vcc pin
becomes lower than Vdet3.)
4. When the VC13 bit in the VCR1 register and D42 bit in the D4INT register are used or the D40 bit is set to
“1” (voltage down detection interrupt enable), set the VC27 bit to “1” (voltage down detection circuit enable).
5. This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
6. The detection circuit does not start operation until td(E-A) elapses after the VC26 bit, or VC27 bit are set to
“1”.
D
4
0
V
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t
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(1)
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r
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s
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t
D
4
I
N
T0
0
1
F
1
6
0
0
1
6
interrupt enable bit (5)
Bit name
B
i
t
s
y
m
b
o
l
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
0 :
Disable
1 :
Enable
D
4
1
STOP mode deactivation
control bit
(4)
0
:
D
i
s
a
b
l
e
(
d
o
n
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t
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t
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p
m
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)
1
:
E
n
a
b
l
e
(
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t
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v
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t
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f
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p
m
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)
D
4
2
Voltage change detection flag
(2)
0: Not detected
1: Vdet4 passing detection
D43
WDT overflow detect flag
0
:
N
o
t
d
e
t
e
c
t
e
d
1
:
D
e
t
e
c
t
e
d
DF0
Sampling clock select bit
0
0
:
C
P
U
c
l
o
c
k
d
i
v
i
d
e
d
b
y
8
0
1
:
C
P
U
c
l
o
c
k
d
i
v
i
d
e
d
b
y
1
6
1
0
:
C
P
U
c
l
o
c
k
d
i
v
i
d
e
d
b
y
3
2
1
1
:
C
P
U
c
l
o
c
k
d
i
v
i
d
e
d
b
y
6
4
D
F
1
b
5
b
4
RW
RW
RW
RW
RW
R
W
R
W
(b7-b6)
Function
Nothing is assigned. When write, set to “0”. When read, its
content is “0”.
NOTES:
1. Write to this register after setting the PRC3 bit in the PRCR register to “1” (write enable).
2. Useful when the VC27 bit in the VCR2 register is set to “1” (voltage down detection circuit enabled). If the
VC27 bit is set to “0” (voltage down detection circuit disable), the D42 bit is set to “0” (Not detect).
3. This bit is set to “0” by writing a “0” in a program. (Writing a “1” has no effect.)
4. If the voltage down detection interrupt needs to be used to get out of stop mode again after once used for
that purpose, reset the D41 bit by writing a “0” and then a “1”.
5. The D40 bit is effective when the VC27 bit in the VCR2 register is set to “1”. To set the D40 bit to “1”, follow
the procedure described below.
(1) Set the VC27 bit to “1”.
(2) Wait for td(E-A) until the detection circuit is actuated.
(3) Wait for the sampling time (refer to “Table 5.5.1.2 Sampling Clock Periods”).
(4) Set the D40 bit to “1”.
(3)
(3)