Datasheet
Table Of Contents
- Notes regarding these materials
- General Precautions in the Handling of MPU/MCU Products
- How to Use This Manual
- Table of Contents
- Quick Reference by Address B-
- 1. Overview
- 2. Central Processing Unit (CPU)
- 2.1 Data Registers (R0, R1, R2 and R3)
- 2.2 Address Registers (A0 and A1)
- 2.3 Frame Base Register (FB)
- 2.4 Interrupt Table Register (INTB)
- 2.5 Program Counter (PC)
- 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
- 2.7 Static Base Register (SB)
- 2.8 Flag Register (FLG)
- 2.8.1 Carry Flag (C Flag)
- 2.8.2 Debug Flag (D Flag)
- 2.8.3 Zero Flag (Z Flag)
- 2.8.4 Sign Flag (S Flag)
- 2.8.5 Register Bank Select Flag (B Flag)
- 2.8.6 Overflow Flag (O Flag)
- 2.8.7 Interrupt Enable Flag (I Flag)
- 2.8.8 Stack Pointer Select Flag (U Flag)
- 2.8.9 Processor Interrupt Priority Level (IPL)
- 2.8.10 Reserved Area
- 3. Memory
- 4. Special Function Registers (SFRs)
- 5. Reset
- 6. Processor Mode
- 7. Clock Generation Circuit
- 8. Protection
- 9. Interrupt
- 10. Watchdog Timer
- 11. DMAC
- 12. Timer
- 13. Serial I/O
- 14. A/D Converter
- 15. CRC Calculation Circuit
- 16. Programmable I/O Ports
- 16.1 Port Pi Direction Register (PDi Register, i = 1, 6 to 10)
- 16.2 Port Pi Register (Pi Register, i = 1, 6 to 10)
- 16.3 Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers)
- 16.4 Port Control Register
- 16.5 Pin Assignment Control register (PACR)
- 16.6 Digital Debounce function
- 17. Flash Memory Version
- 17.1 Flash Memory Performance
- 17.2 Memory Map
- 17.3 Functions To Prevent Flash Memory from Rewriting
- 17.4 CPU Rewrite Mode
- 17.5 Register Description
- 17.6 Precautions in CPU Rewrite Mode
- 17.6.1 Operation Speed
- 17.6.2 Prohibited Instructions
- 17.6.3 Interrupts
- 17.6.4 How to Access
- 17.6.5 Writing in the User ROM Space
- 17.6.6 DMA Transfer
- 17.6.7 Writing Command and Data
- 17.6.8 Wait Mode
- 17.6.9 Stop Mode
- 17.6.10 Low Power Consumption Mode and On-chip Oscillator-Low Power Consumption Mode
- 17.7 Software Commands
- 17.8 Status Register
- 17.9 Standard Serial I/O Mode
- 17.10 Parallel I/O Mode
- 18. Electrical Characteristics
- 19. Usage Notes
- 19.1 SFR
- 19.2 PLL Frequency Synthesizer
- 19.3 Power Control
- 19.4 Protect
- 19.5 Interrupts
- 19.6 DMAC
- 19.7 Timer
- 19.8 Serial I/O
- 19.9 A/D Converter
- 19.10 Programmable I/O Ports
- 19.11 Electric Characteristic Differences Between Mask ROM
- 19.12 Mask ROM Version
- 19.13 Flash Memory Version
- 19.13.1 Functions to Inhibit Rewriting Flash Memory
- 19.13.2 Stop mode
- 19.13.3 Wait mode
- 19.13.4 Low power dissipation mode, on-chip oscillator low power dissipation mode
- 19.13.5 Writing command and data
- 19.13.6 Program Command
- 19.13.7 Operation speed
- 19.13.8 Instructions prohibited in EW0 Mode
- 19.13.9 Interrupts
- 19.13.10 How to access
- 19.13.11 Writing in the user ROM area
- 19.13.12 DMA transfer
- 19.13.13 Regarding Programming/Erasure Times and Execution Time
- 19.13.14 Definition of Programming/Erasure Times
- 19.13.15 Flash Memory Version Electrical Characteristics 10,000 E/W cycle product
- 19.13.16 Boot Mode
- 19.14 Noise
- 19.15 Instruction for a Device Use
- Appendix 1. Package Dimensions
- Appendix 2. Functional Difference
- Register Index
- REVISION HISTORY
4. SFRs
page 24
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
923fo7002,51.beF00.2.veR
0020-2020B90JER
Table 4.5 SFR Information(5)
(1)
038016
038116
038216
038316
038416
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
039E16
039F16
03A016
03A116
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16
03B016
03B116
03B216
03B316
03B416
03B516
03B616
03B716
03B816
03B916
03BA16
03BB16
03BC16
03BD16
03BE16
03BF16
NOTE:
1. Blank spaces are reserved. No access is allowed.
X : Undefined
Address Register Symbol After reset
Count start flag TABSR 00
16
Clock prescaler reset flag CPSRF 0XXXXXXX
2
One-shot start flag ONSF 00
16
Trigger select register TRGSR 00
16
Up-dowm flag UDF 00
16
Timer A0 register TA0 XX
16
XX
16
Timer A1 register TA1 XX
16
XX
16
Timer A2 register TA2 XX
16
XX
16
Timer A3 register TA3 XX
16
XX
16
Timer A4 register TA4 XX
16
XX
16
Timer B0 register TB0 XX
16
XX
16
Timer B1 register TB1 XX
16
XX
16
Timer B2 register TB2 XX
16
XX
16
Timer A0 mode register TA0MR 00
16
Timer A1 mode register TA1MR 00
16
Timer A2 mode register TA2MR 00
16
Timer A3 mode register TA3MR 00
16
Timer A4 mode register TA4MR 00
16
Timer B0 mode register TB0MR 00XX0000
2
Timer B1 mode register TB1MR 00XX0000
2
Timer B2 mode register TB2MR 00XX0000
2
Timer B2 special mode register TB2SC X0000000
2
UART0 transmit/receive mode register U0MR 00
16
UART0 bit rate register U0BRG XX
16
UART0 transmit buffer register U0TB XXXXXXXX
2
XXXXXXXX
2
UART0 transmit/receive control register 0 U0C0 00001000
2
UART0 transmit/receive control register 1 U0C1 00000010
2
UART0 receive buffer register U0RB XXXXXXXX
2
XXXXXXXX
2
UART1 transmit/receive mode register U1MR 00
16
UART1 bit rate register U1BRG XX
16
UART1 transmit buffer register U1TB XXXXXXXX
2
XXXXXXXX
2
UART1 transmit/receive control register 0 U1C0 00001000
2
UART1 transmit/receive control register 1 U1C1 00000010
2
UART1 receive buffer register U1RB XXXXXXXX
2
XXXXXXXX
2
UART transmit/receive control register 2 UCON X0000000
2
CRC snoop address register CRCSAR XX
16
00XXXXXX
2
CRC mode register CRCMR 0XXXXXX0
2
DMA0 request cause select register DM0SL 00
16
DMA1 request cause select register DM1SL 00
16
CRC data register CRCD XX
16
XX
16
CRC input register CRCIN XX
16