Datasheet

2. CPU
page 17
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2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The register bank is comprised of seven registers (R0, R1, R2, R3,
A0, A1 and FB) out of 13 registers. There are two sets of register bank.
Figure 2.1. CPU Register
2.1 Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit
data register (R2R0). R3R1 is the same as R2R0.
2.2 Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address regis-
ter relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the same as
A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
Data registers (1)
Address registers (1)
Frame base registers (1)
Program counter
Interrupt table register
User stack pointer
Interrupt stack pointer
Static base register
Flag register
NOTE:
1. These registers comprise a register bank. There are two register banks.
R0H(R0's high bits)
b15
b8 b7 b0
R3
INTBH
USP
ISP
SB
R0L(R0's low bits)
R1H(R1's high bits)
R1L(R1's low bits)
R2
b31
R3
R2
A1
A0
FB
b19
INTBL
b15
b0
PC
b19
b0
b15
b0
FLG
b15
b0
b15
b0
b7
b8
b
Reserved area
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
The upper 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.