Datasheet
Table Of Contents
- Notes regarding these materials
- General Precautions in the Handling of MPU/MCU Products
- How to Use This Manual
- Table of Contents
- Quick Reference by Address B-
- 1. Overview
- 2. Central Processing Unit (CPU)
- 2.1 Data Registers (R0, R1, R2 and R3)
- 2.2 Address Registers (A0 and A1)
- 2.3 Frame Base Register (FB)
- 2.4 Interrupt Table Register (INTB)
- 2.5 Program Counter (PC)
- 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
- 2.7 Static Base Register (SB)
- 2.8 Flag Register (FLG)
- 2.8.1 Carry Flag (C Flag)
- 2.8.2 Debug Flag (D Flag)
- 2.8.3 Zero Flag (Z Flag)
- 2.8.4 Sign Flag (S Flag)
- 2.8.5 Register Bank Select Flag (B Flag)
- 2.8.6 Overflow Flag (O Flag)
- 2.8.7 Interrupt Enable Flag (I Flag)
- 2.8.8 Stack Pointer Select Flag (U Flag)
- 2.8.9 Processor Interrupt Priority Level (IPL)
- 2.8.10 Reserved Area
- 3. Memory
- 4. Special Function Registers (SFRs)
- 5. Reset
- 6. Processor Mode
- 7. Clock Generation Circuit
- 8. Protection
- 9. Interrupt
- 10. Watchdog Timer
- 11. DMAC
- 12. Timer
- 13. Serial I/O
- 14. A/D Converter
- 15. CRC Calculation Circuit
- 16. Programmable I/O Ports
- 16.1 Port Pi Direction Register (PDi Register, i = 1, 6 to 10)
- 16.2 Port Pi Register (Pi Register, i = 1, 6 to 10)
- 16.3 Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers)
- 16.4 Port Control Register
- 16.5 Pin Assignment Control register (PACR)
- 16.6 Digital Debounce function
- 17. Flash Memory Version
- 17.1 Flash Memory Performance
- 17.2 Memory Map
- 17.3 Functions To Prevent Flash Memory from Rewriting
- 17.4 CPU Rewrite Mode
- 17.5 Register Description
- 17.6 Precautions in CPU Rewrite Mode
- 17.6.1 Operation Speed
- 17.6.2 Prohibited Instructions
- 17.6.3 Interrupts
- 17.6.4 How to Access
- 17.6.5 Writing in the User ROM Space
- 17.6.6 DMA Transfer
- 17.6.7 Writing Command and Data
- 17.6.8 Wait Mode
- 17.6.9 Stop Mode
- 17.6.10 Low Power Consumption Mode and On-chip Oscillator-Low Power Consumption Mode
- 17.7 Software Commands
- 17.8 Status Register
- 17.9 Standard Serial I/O Mode
- 17.10 Parallel I/O Mode
- 18. Electrical Characteristics
- 19. Usage Notes
- 19.1 SFR
- 19.2 PLL Frequency Synthesizer
- 19.3 Power Control
- 19.4 Protect
- 19.5 Interrupts
- 19.6 DMAC
- 19.7 Timer
- 19.8 Serial I/O
- 19.9 A/D Converter
- 19.10 Programmable I/O Ports
- 19.11 Electric Characteristic Differences Between Mask ROM
- 19.12 Mask ROM Version
- 19.13 Flash Memory Version
- 19.13.1 Functions to Inhibit Rewriting Flash Memory
- 19.13.2 Stop mode
- 19.13.3 Wait mode
- 19.13.4 Low power dissipation mode, on-chip oscillator low power dissipation mode
- 19.13.5 Writing command and data
- 19.13.6 Program Command
- 19.13.7 Operation speed
- 19.13.8 Instructions prohibited in EW0 Mode
- 19.13.9 Interrupts
- 19.13.10 How to access
- 19.13.11 Writing in the user ROM area
- 19.13.12 DMA transfer
- 19.13.13 Regarding Programming/Erasure Times and Execution Time
- 19.13.14 Definition of Programming/Erasure Times
- 19.13.15 Flash Memory Version Electrical Characteristics 10,000 E/W cycle product
- 19.13.16 Boot Mode
- 19.14 Noise
- 19.15 Instruction for a Device Use
- Appendix 1. Package Dimensions
- Appendix 2. Functional Difference
- Register Index
- REVISION HISTORY
REVISION HISTORY M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Hardware Manual
Rev. Date Description
Page Summary
C-3
1 added
CRC Calculation Circuit
213 •15.1 CRC Snoop Description partially modified
214 •Figure 15.2 CRCSAR Register note 1 added
Programable I/O Ports
216 •16.3 Pull-up Control Register 0 to Pull-up Control Register 2 description
modified
217 •16.6 Digital Debounce function equation modified
218 - 221 •Figure 16.1 I/O Ports (1) to 16.4 I/O Ports (4) modified
227 •Figure 16.6.1 NDDR and P17DDR Registers equation modified, note 2 modi-
fied
Flash Memory Version
231 •17.1.1 Boot Mode newly added
232 •17.2 Memory Map partially deleted
235 •17.3.1 ROM Code Protect Function description modified
236 •Figure 17.3.1.1 ROMCP Address modified
237 •Table 17.4.1 EW0 Mode and EW1 Mode note 2 mark deleted
239 •17.5.1 Flash Memory Control Register 0 Description about low power con-
sumption mode or on-chip oscillator low-power consumption mode is entered
partially modified
240 •17.5.2 Flash Memory Control Register 1 Description about FMR17 bit modified
241 •Figure 17.5.1 FMR0 Register note 3 modified, FMR1 Register: bit map modi-
fied
242 •Figure 17.5.2 FMR4 Register note 2 modified
243 •Figure 17.5.1.2 Setting and Resetting of EW1 Mode note for single-chip mode
deleted, note 3 for FMR11 bit added
Electrical Characteristics
261 •Table 18.1 Absolute Maximum Ratings Rated value modifed, note 1 added
262 •Table 18.2 Recommended Operating Conditions value partially added, fig-
ures in note 4 partially added
263 •Table 18.3 A/D Conversion Characteristics note 4 modified
264 •Table 18.4 and Table 18.5 Flash Memory Version Electrical Characteristic
note 4 partially added, note 6 and note 7 modified
265 •Table 18.6 Voltage Detection Circuit Electrical Characteristics conditions modi-
fied
•Figure for td(P-R) and td(ROC) modified
267 •Table 18.9 eElectrical Characteristics (2) flash memory’s value for M16C/26B
added, note 5 deleted
274 •Table 18.24 Electrical Characteristics (2) note 5 deleted