Datasheet
Table Of Contents
- Notes regarding these materials
- General Precautions in the Handling of MPU/MCU Products
- How to Use This Manual
- Table of Contents
- Quick Reference by Address B-
- 1. Overview
- 2. Central Processing Unit (CPU)
- 2.1 Data Registers (R0, R1, R2 and R3)
- 2.2 Address Registers (A0 and A1)
- 2.3 Frame Base Register (FB)
- 2.4 Interrupt Table Register (INTB)
- 2.5 Program Counter (PC)
- 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
- 2.7 Static Base Register (SB)
- 2.8 Flag Register (FLG)
- 2.8.1 Carry Flag (C Flag)
- 2.8.2 Debug Flag (D Flag)
- 2.8.3 Zero Flag (Z Flag)
- 2.8.4 Sign Flag (S Flag)
- 2.8.5 Register Bank Select Flag (B Flag)
- 2.8.6 Overflow Flag (O Flag)
- 2.8.7 Interrupt Enable Flag (I Flag)
- 2.8.8 Stack Pointer Select Flag (U Flag)
- 2.8.9 Processor Interrupt Priority Level (IPL)
- 2.8.10 Reserved Area
- 3. Memory
- 4. Special Function Registers (SFRs)
- 5. Reset
- 6. Processor Mode
- 7. Clock Generation Circuit
- 8. Protection
- 9. Interrupt
- 10. Watchdog Timer
- 11. DMAC
- 12. Timer
- 13. Serial I/O
- 14. A/D Converter
- 15. CRC Calculation Circuit
- 16. Programmable I/O Ports
- 16.1 Port Pi Direction Register (PDi Register, i = 1, 6 to 10)
- 16.2 Port Pi Register (Pi Register, i = 1, 6 to 10)
- 16.3 Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers)
- 16.4 Port Control Register
- 16.5 Pin Assignment Control register (PACR)
- 16.6 Digital Debounce function
- 17. Flash Memory Version
- 17.1 Flash Memory Performance
- 17.2 Memory Map
- 17.3 Functions To Prevent Flash Memory from Rewriting
- 17.4 CPU Rewrite Mode
- 17.5 Register Description
- 17.6 Precautions in CPU Rewrite Mode
- 17.6.1 Operation Speed
- 17.6.2 Prohibited Instructions
- 17.6.3 Interrupts
- 17.6.4 How to Access
- 17.6.5 Writing in the User ROM Space
- 17.6.6 DMA Transfer
- 17.6.7 Writing Command and Data
- 17.6.8 Wait Mode
- 17.6.9 Stop Mode
- 17.6.10 Low Power Consumption Mode and On-chip Oscillator-Low Power Consumption Mode
- 17.7 Software Commands
- 17.8 Status Register
- 17.9 Standard Serial I/O Mode
- 17.10 Parallel I/O Mode
- 18. Electrical Characteristics
- 19. Usage Notes
- 19.1 SFR
- 19.2 PLL Frequency Synthesizer
- 19.3 Power Control
- 19.4 Protect
- 19.5 Interrupts
- 19.6 DMAC
- 19.7 Timer
- 19.8 Serial I/O
- 19.9 A/D Converter
- 19.10 Programmable I/O Ports
- 19.11 Electric Characteristic Differences Between Mask ROM
- 19.12 Mask ROM Version
- 19.13 Flash Memory Version
- 19.13.1 Functions to Inhibit Rewriting Flash Memory
- 19.13.2 Stop mode
- 19.13.3 Wait mode
- 19.13.4 Low power dissipation mode, on-chip oscillator low power dissipation mode
- 19.13.5 Writing command and data
- 19.13.6 Program Command
- 19.13.7 Operation speed
- 19.13.8 Instructions prohibited in EW0 Mode
- 19.13.9 Interrupts
- 19.13.10 How to access
- 19.13.11 Writing in the user ROM area
- 19.13.12 DMA transfer
- 19.13.13 Regarding Programming/Erasure Times and Execution Time
- 19.13.14 Definition of Programming/Erasure Times
- 19.13.15 Flash Memory Version Electrical Characteristics 10,000 E/W cycle product
- 19.13.16 Boot Mode
- 19.14 Noise
- 19.15 Instruction for a Device Use
- Appendix 1. Package Dimensions
- Appendix 2. Functional Difference
- Register Index
- REVISION HISTORY
REVISION HISTORY M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Hardware Manual
Rev. Date Description
Page Summary
C-2
77
______
•9.7 NMI Interrupt Description partially added
78 •Table 9.9.1 Value of the PC that is saved to the stack area when an address
match interrupt request is accepted modified, note 1 added
Watchdog Timer
- •Section of Cold Start/Warm Start deleted
80 •Description partially added
•Figure 10.1 Watchdog Timer Block Diagram partially modified
81 •Figure 10.2 WDC Register and WDTS Register notes deleted, WDC5 bit de-
leted
•10.1 Count source protective mode description partially added
Timer
108 •Description about A/D trigger mode modified
•Figure 12.2.1 Timber B Block Diagram A/D trigger mode added
115 •12.2.4 A/D Trigger Mode Description modified
121 •Figure 12.3.4 IDB0 Register, IDB1 Register, DTT Register, and ICTB2 Regis-
ter modified
123 •Figure 12.3.6 TB2SC Register modified, note 4 added
131 •Figure 12.3.2.2 TPRC Register bit map modified
Serial I/O
133 •Figure 13.1.1 Block Diagram of UARTi (i = 0 to 2) PLL clock added
136 •Figure 13.1.4 U0TB to U2TB Registers, U0RB to U2RB Registers, U0BRG to
U2BRG Registers modified, note 3 for UiBRG added
138 •Figure 13.1.6 U0C0 to U2C0 Registers Note 2 modified, note 7 added
139 •Figure 13.1.7 PACR Register note 1 modified
142 •Table 13.1.1.1 Clock Synchronous Serial I/O Mode Specification note 2 modi-
fied
145 •Figure 13.1.1.1 Typical Transmit/Receive Timings in Clock Synchronous
Serial I/O Mode partially modified
150 •Table 13.1.2.1 UART Mode Specifications Note 1 modified
154 •Figure 13.1.2.2 Receive Operation Figure modified
158 •Table 13.1.3.1 I
2
C bus Mode Specifications note 2 modified
168 •Table 13.1.4.1 Special Mode 2 Specifications note 2 modified
175 •Table 13.1.6.1 SIM Mode Specifications note 1 modified
177 •Figure 13.1.6.1 Transmit and Receive Timing in SIM Mode timing modified
A/D Converter
180 •Table 14.1 A/D Converter Performance note 2 partially added
183 •Table 14.2 A/D Conversion Frequency Select note 1 partially added
205 •Table 14.1.8.1 Delayed Trigger Mode 1 Specifications note 1 modified
212 •Figure 14.5.1 Analog Input Pin and External Sensor Equivalent Circuit note