Datasheet

page 317
19. Usage Notes
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19.10 Programmable I/O Ports
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1. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to “1”
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(three-phase output forcible cutoff by input on SD pin enabled), the P72 to P75, P80 and P81 pins go to
a high-impedance state.
2. The input threshold voltage of pins differs between programmable input/output ports and peripheral
functions.
Therefore, if any pin is shared by a programmable input/output port and a peripheral function and the
input level at this pin is outside the range of recommended operating conditions VIH and VIL (neither
“high” nor “low”), the input level may be determined differently depending on which side—the program-
mable input/output port or the peripheral function—is currently selected.
3. When the INV03 bit in the INVC0 register is "1"(three-phase motor control timer output enabled), an "L"
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input on the P85 /NMI/SD pin, has the following effect:
•When the IVPCR1 bit in the TB2SC register is set to “1” (three-phase output forcible cutoff by input
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on the SD pin enabled), the U/ U/ V/ V/ W/ W pins go to a high-impedance state.
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•When the IVPCR1 bit is set to “0” (three-phase output forcible cutoff by input on SD pin
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disabled), the U/ U/ V/ V/ W/ W pins go to a normal port.
Therefore, the P85 pin can not be used as programmable I/O port when the INV03 bit is set to "1".
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When the SD function isn't used, set PD85 to “0” (Input) and pull the P85 /NMI/SD pin to “H” externally.