Datasheet

page 305
19. Usage Notes
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______
19.5.5 INT Interrupt
1. Either an “L” level of at least tW(INH) or an “H” level of at least tW(INL) width is necessary for the signal
_______ _______
input to pins INT0 through INT5 regardless of the CPU operation clock.
2. If the POL bit in the INT0IC to INT5IC registers or the IFSR7 to IFSR0 bits in the IFSR register are
changed, the IR bit may inadvertently set to 1 (interrupt requested). Be sure to clear the IR bit to 0
(interrupt not requested) after changing any of those register bits.
3. When using the INT5 interrupt for exiting stop mode, set the P17DDR register to “FF16” (disable digital
debounce filter) before entering stop mode.
Figure 19.2. Procedure for Changing the Interrupt Generate Factor
Changing the interrupt source
Disable interrupts (2, 3)
Use the MOV instruction to clear the IR bit to “0” (interrupt not requested) (3)
Change the interrupt generate factor (including a mode change of peripheral function)
Enable interrupts (2, 3)
End of change
IR bit: A bit in the interrupt control register for the interrupt whose interrupt generate factor is to
be changed
NOTES:
1. The above settings must be executed individually. Do not execute two or more settings simultaneously
(using one instruction).
2. Use the I flag for the INTi interrupt (i = 0 to 5).
For the interrupts from peripheral functions other than the INTi interrupt, turn off the peripheral function that
is the source of the interrupt in order not to generate an interrupt request before changing the interrupt
generate factor. In this case, if the maskable interrupts can all be disabled without causing a problem, use
the I flag. Otherwise, use the corresponding
3. Refer to 19.5.6 Rewrite the Interrupt Control Register for details about the instructions to use and the
notes to be taken for instruction execution.