Datasheet

page 302
19. Usage Notes
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0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
5. Wait until the main clock oscillation stabilization time, before switching the CPU clock source to the
main clock.
Similarly, wait until the sub clock oscillates stably before switching the CPU clock source to the sub
clock.
6. Suggestions to reduce power consumption
(a) Ports
The processor retains the state of each I/O port even when it goes to wait mode or to stop mode. A
current flows in active I/O ports. A dash current may flow through the input ports in high impedance
state, if the input is floating. When entering wait mode or stop mode, set non-used ports to input and
stabilize the potential.
(b) A/D converter
When A/D conversion is not performed, set the VCUT bit in the ADCON1 register to “0” (no VREF
connection). When A/D conversion is performed, start the A/D conversion at least 1 µs or longer after
setting the VCUT bit to “1” (VREF connection).
(c) Stopping peripheral functions
Use the CM02 bit in the CM0 register to stop the unnecessary peripheral functions during wait mode.
However, because the peripheral function clock (fC32) generated from the sub-clock does not stop,
this measure is not conducive to reducing the power consumption of the chip. If low speed mode or
low power dissipation mode is to be changed to wait mode, set the CM02 bit to “0” (do not stop
peripheral function clocks in wait mode), before changing wait mode.
(d) Switching the oscillation-driving capacity
Set the driving capacity to “LOW” when oscillation is stable.