Datasheet
Table Of Contents
- Notes regarding these materials
- General Precautions in the Handling of MPU/MCU Products
- How to Use This Manual
- Table of Contents
- Quick Reference by Address B-
- 1. Overview
- 2. Central Processing Unit (CPU)
- 2.1 Data Registers (R0, R1, R2 and R3)
- 2.2 Address Registers (A0 and A1)
- 2.3 Frame Base Register (FB)
- 2.4 Interrupt Table Register (INTB)
- 2.5 Program Counter (PC)
- 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
- 2.7 Static Base Register (SB)
- 2.8 Flag Register (FLG)
- 2.8.1 Carry Flag (C Flag)
- 2.8.2 Debug Flag (D Flag)
- 2.8.3 Zero Flag (Z Flag)
- 2.8.4 Sign Flag (S Flag)
- 2.8.5 Register Bank Select Flag (B Flag)
- 2.8.6 Overflow Flag (O Flag)
- 2.8.7 Interrupt Enable Flag (I Flag)
- 2.8.8 Stack Pointer Select Flag (U Flag)
- 2.8.9 Processor Interrupt Priority Level (IPL)
- 2.8.10 Reserved Area
- 3. Memory
- 4. Special Function Registers (SFRs)
- 5. Reset
- 6. Processor Mode
- 7. Clock Generation Circuit
- 8. Protection
- 9. Interrupt
- 10. Watchdog Timer
- 11. DMAC
- 12. Timer
- 13. Serial I/O
- 14. A/D Converter
- 15. CRC Calculation Circuit
- 16. Programmable I/O Ports
- 16.1 Port Pi Direction Register (PDi Register, i = 1, 6 to 10)
- 16.2 Port Pi Register (Pi Register, i = 1, 6 to 10)
- 16.3 Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers)
- 16.4 Port Control Register
- 16.5 Pin Assignment Control register (PACR)
- 16.6 Digital Debounce function
- 17. Flash Memory Version
- 17.1 Flash Memory Performance
- 17.2 Memory Map
- 17.3 Functions To Prevent Flash Memory from Rewriting
- 17.4 CPU Rewrite Mode
- 17.5 Register Description
- 17.6 Precautions in CPU Rewrite Mode
- 17.6.1 Operation Speed
- 17.6.2 Prohibited Instructions
- 17.6.3 Interrupts
- 17.6.4 How to Access
- 17.6.5 Writing in the User ROM Space
- 17.6.6 DMA Transfer
- 17.6.7 Writing Command and Data
- 17.6.8 Wait Mode
- 17.6.9 Stop Mode
- 17.6.10 Low Power Consumption Mode and On-chip Oscillator-Low Power Consumption Mode
- 17.7 Software Commands
- 17.8 Status Register
- 17.9 Standard Serial I/O Mode
- 17.10 Parallel I/O Mode
- 18. Electrical Characteristics
- 19. Usage Notes
- 19.1 SFR
- 19.2 PLL Frequency Synthesizer
- 19.3 Power Control
- 19.4 Protect
- 19.5 Interrupts
- 19.6 DMAC
- 19.7 Timer
- 19.8 Serial I/O
- 19.9 A/D Converter
- 19.10 Programmable I/O Ports
- 19.11 Electric Characteristic Differences Between Mask ROM
- 19.12 Mask ROM Version
- 19.13 Flash Memory Version
- 19.13.1 Functions to Inhibit Rewriting Flash Memory
- 19.13.2 Stop mode
- 19.13.3 Wait mode
- 19.13.4 Low power dissipation mode, on-chip oscillator low power dissipation mode
- 19.13.5 Writing command and data
- 19.13.6 Program Command
- 19.13.7 Operation speed
- 19.13.8 Instructions prohibited in EW0 Mode
- 19.13.9 Interrupts
- 19.13.10 How to access
- 19.13.11 Writing in the user ROM area
- 19.13.12 DMA transfer
- 19.13.13 Regarding Programming/Erasure Times and Execution Time
- 19.13.14 Definition of Programming/Erasure Times
- 19.13.15 Flash Memory Version Electrical Characteristics 10,000 E/W cycle product
- 19.13.16 Boot Mode
- 19.14 Noise
- 19.15 Instruction for a Device Use
- Appendix 1. Package Dimensions
- Appendix 2. Functional Difference
- Register Index
- REVISION HISTORY
1. Overview
page 11
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0020-2020B90JER
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24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
P9
2
/TB2
IN
/AN
32
P9
1
/TB1
IN
/AN
31
CNV
SS
P1
7
/INT
5
/IDU
P1
6
/INT
4
/IDW
P1
5
/INT
3
/AD
TRG
/IDV
P10
7
/AN
7
/KI
3
P7
0
/TxD
2
/TA
0OUT
/SDA
2
/CTS
1
/RTS
1
/CTS
0
/CLKS
1
X
OUT
V
SS
X
IN
P8
5
/NMI/SD
V
CC
P6
7
/TxD
1
P6
6
/RxD
1
P6
5
/CLK
1
RESET
P7
1
/RxD
2
/TA0
IN
/SCL
2
/CLK
1
P7
2
/CLK
2
/TA1
OUT
/V/RxD
1
P7
3
/CTS
2
/RTS
2
/TA1
IN
/V/TxD
1
P7
4
/TA2
OUT
/W
P7
5
/TA2
IN
/W
P7
6
/TA3
OUT
P7
7
/TA3
IN
P8
0
/TA4
OUT
/U
P8
1
/TA4
IN
/U
P8
2
/INT
0
P8
3
/INT
1
P6
4
/CTS
1
/RTS
1
/CTS
0
/CLKS
1
P6
3
/TxD
0
P6
2
/RxD
0
P6
1
/CLK
0
P6
0
/CTS
0
/RTS
0
P9
0
/TB0
IN
/AN
30
/CLK
OUT
P8
7
/X
CIN
P8
6
/X
COUT
P10
6
/AN
6
/KI
2
P10
5
/AN
5
/KI
1
P10
4
/AN
4
/KI
0
P10
3
/AN
3
P10
2
/AN
2
P10
1
/AN
1
AV
ss
P10
0
/AN
0
V
REF
AV
cc
P9
3
/AN
24
P8
4
/INT
2
/ZP
NOTE:
1. Set PACR2 to PACR0 bit in the PACR register
to "100
2
" before you input and output it after
resetting to each pin. When the PACR register
isn't set up, the input and output function of
some of the
p
ins are disabled.
Package: PLQP0048KB-A (48P6Q)
1.5 Pin Assignments
Figures 1.6 and 1.7 show the Pin Assignments (top view).
Figure 1.6 Pin Assignment for 48-Pin Package (Top View)