Datasheet

17. Flash Memory Version
page 252
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0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
17.8.4 Full Status Check
When an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to “1”, indicating occur-
rence of each specific error. Therefore, execution results can be verified by checking these status bits
(full status check). Table 17.8.4.1 shows errors and the status of FMR0 register. Figure 17.8.4.1
shows a flow chart of the full status check and handling procedure for each error.
Table 17.8.4.1. Errors and FMR0 Register Status
FMR0 register
(SRD register)
status Error Error occurrence condition
FMR07 FMR06
(SR5) (SR4)
1 1 Command • When any commands are not written correctly
sequence error • A value other than ‘xxD016’ or ‘xxFF16’ is written in the second
bus cycle of the block erase command
(1)
• When the block erase command is executed on protected blocks
• When the program command is executed on protected blocks
1 0 Erase error • When the block erase command is executed on unprotected
blocks but the blocks are not automatically erased correctly
0 1 Program error • When the program command is executed on unprotected blocks
but the blocks are not automatically programmed correctly.
NOTE:
1. The flash memory enters read array mode by writing command code ‘xxFF16’ in the second bus
cycle of these commands. The command code written in the first bus cycle becomes invalid.