Datasheet

17. Flash Memory Version
page 236
923fo7002,51.beF00.2.veR
0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
Figure 17.3.1.1. ROMCP Address
Figure 17.3.2.1. Address for ID Code Stored
Symbol Address Factory Setting
ROMCP 0FFFFF
16 FF 16
(4)
ROM Code Protect Control Address
(5)
Bit Name Function
Bit Symbol
b7 b6 b5 b4 b3 b2 b1 b0
00:
01:
10:
11: Disables protect
ROM Code Protect Level
1 Set Bit
(1, 2, 3, 4)
ROMCP1
b7 b6
11
Reserved Bit
Set to 1
Enables protect
}
NOTES:
1. When the ROM code protect is active by the ROMCP1 bit setting, the flash memory is protected
against reading or rewriting in parallel I/O mode.
2. Set the bit 5 to bit 0 to 111111
2 when the ROMCP1 bit is set to a value other than 11 2 . If the bit 5 to bit
0 are set to values other than 111111
2 , the ROM code protection may not become active by setting the
ROMCP1 bit to a value other than 11
2 .
3. To make the ROM code protection inactive, erase a block including the ROMCP address in standard
serial I/O mode or CPU rewrite mode.
4. The ROMCP address is set to FF
16 when a block, including the ROMCP address, is erased.
5. When a value of the ROMCP address is 00
16 or FF 16 , the ROM code protect function is disabled.
11
RW
RW
RW
RW
(b5-b0)
11
Reset vector
Watchdog timer vector
Single step vector
Address match vector
BRK instruction vector
Overflow vector
Undefined instruction vector
ID7
ID6
ID5
ID4
ID3
ID2
ID1
DBC vector
NMI vector
0FFFFF 16 to 0FFFFC 16
0FFFFB 16 to 0FFFF8 16
0FFFF7 16 to 0FFFF4 16
0FFFF3 16 to 0FFFF0 16
0FFFEF 16 to 0FFFEC 16
0FFFEB 16 to 0FFFE8 16
0FFFE7 16 to 0FFFE4 16
0FFFE3 16 to 0FFFE0 16
0FFFDF 16 to 0FFFDC 16
4 bytes
Address
ROMCP