Datasheet

14. A/D Converter
page 198
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0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
Figure 14.1.6.3 ADTRGCON Register in Simultaneous Sample Sweep Mode
A/D trigger control register
(1)
Symbol Address After reset
ADTRGCON 03D216 0016
b7 b6 b5 b4 b3 b2 b1 b0
A/D Operation Mode
Select Bit 2
Bit symbol Bit name Function RW
SSE
A/D Operation Mode
Select Bit 3
AN1 Trigger Select Bit
HPTRG1
DTE
HPTRG0
RW
RW
RW
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b4)
AN0 Trigger Select Bit
NOTE:
1. If ADTRGCON register is rewritten during A/D conversion, the conversion result will be indeterminate.
0
0 : Any mode other than delayed trigger
mode 0,1
1 : Simultaneous sample sweep mode
or delayed trigger mode 0, 1
10
Refer to Table 14.1.6.2 Trigger Select
Bit Setting in Simultaneous Sample
Sweep Mode
Set to "0" in simultaneous sample
sweep mode
Table 14.1.6.2 Trigger Select Bit Setting in Simultaneous Sample Sweep Mode
TRG HPTRG0TRG1
TRIGGER
0
1
1
1
-
1
0
0
Software trigger
Timer B0 underflow (1)
Timer B2 or Timer B2 interrupt generation frequency
setting counter underflow (2)
AD
TRG
-
-
1
0
NOTE:
1. A count can be started for Timer B2, Timer B2 interrupt generation frequency setting counter underflow or
the INT5 pin falling edge as count start conditions of Timer B0.
2. Select Timer B2 or Timer B2 interrupt generation frequency setting counter using the TB2SEL bit in the
TB2SC register.