Datasheet
Table Of Contents
- Notes regarding these materials
- General Precautions in the Handling of MPU/MCU Products
- How to Use This Manual
- Table of Contents
- Quick Reference by Address B-
- 1. Overview
- 2. Central Processing Unit (CPU)
- 2.1 Data Registers (R0, R1, R2 and R3)
- 2.2 Address Registers (A0 and A1)
- 2.3 Frame Base Register (FB)
- 2.4 Interrupt Table Register (INTB)
- 2.5 Program Counter (PC)
- 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
- 2.7 Static Base Register (SB)
- 2.8 Flag Register (FLG)
- 2.8.1 Carry Flag (C Flag)
- 2.8.2 Debug Flag (D Flag)
- 2.8.3 Zero Flag (Z Flag)
- 2.8.4 Sign Flag (S Flag)
- 2.8.5 Register Bank Select Flag (B Flag)
- 2.8.6 Overflow Flag (O Flag)
- 2.8.7 Interrupt Enable Flag (I Flag)
- 2.8.8 Stack Pointer Select Flag (U Flag)
- 2.8.9 Processor Interrupt Priority Level (IPL)
- 2.8.10 Reserved Area
- 3. Memory
- 4. Special Function Registers (SFRs)
- 5. Reset
- 6. Processor Mode
- 7. Clock Generation Circuit
- 8. Protection
- 9. Interrupt
- 10. Watchdog Timer
- 11. DMAC
- 12. Timer
- 13. Serial I/O
- 14. A/D Converter
- 15. CRC Calculation Circuit
- 16. Programmable I/O Ports
- 16.1 Port Pi Direction Register (PDi Register, i = 1, 6 to 10)
- 16.2 Port Pi Register (Pi Register, i = 1, 6 to 10)
- 16.3 Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers)
- 16.4 Port Control Register
- 16.5 Pin Assignment Control register (PACR)
- 16.6 Digital Debounce function
- 17. Flash Memory Version
- 17.1 Flash Memory Performance
- 17.2 Memory Map
- 17.3 Functions To Prevent Flash Memory from Rewriting
- 17.4 CPU Rewrite Mode
- 17.5 Register Description
- 17.6 Precautions in CPU Rewrite Mode
- 17.6.1 Operation Speed
- 17.6.2 Prohibited Instructions
- 17.6.3 Interrupts
- 17.6.4 How to Access
- 17.6.5 Writing in the User ROM Space
- 17.6.6 DMA Transfer
- 17.6.7 Writing Command and Data
- 17.6.8 Wait Mode
- 17.6.9 Stop Mode
- 17.6.10 Low Power Consumption Mode and On-chip Oscillator-Low Power Consumption Mode
- 17.7 Software Commands
- 17.8 Status Register
- 17.9 Standard Serial I/O Mode
- 17.10 Parallel I/O Mode
- 18. Electrical Characteristics
- 19. Usage Notes
- 19.1 SFR
- 19.2 PLL Frequency Synthesizer
- 19.3 Power Control
- 19.4 Protect
- 19.5 Interrupts
- 19.6 DMAC
- 19.7 Timer
- 19.8 Serial I/O
- 19.9 A/D Converter
- 19.10 Programmable I/O Ports
- 19.11 Electric Characteristic Differences Between Mask ROM
- 19.12 Mask ROM Version
- 19.13 Flash Memory Version
- 19.13.1 Functions to Inhibit Rewriting Flash Memory
- 19.13.2 Stop mode
- 19.13.3 Wait mode
- 19.13.4 Low power dissipation mode, on-chip oscillator low power dissipation mode
- 19.13.5 Writing command and data
- 19.13.6 Program Command
- 19.13.7 Operation speed
- 19.13.8 Instructions prohibited in EW0 Mode
- 19.13.9 Interrupts
- 19.13.10 How to access
- 19.13.11 Writing in the user ROM area
- 19.13.12 DMA transfer
- 19.13.13 Regarding Programming/Erasure Times and Execution Time
- 19.13.14 Definition of Programming/Erasure Times
- 19.13.15 Flash Memory Version Electrical Characteristics 10,000 E/W cycle product
- 19.13.16 Boot Mode
- 19.14 Noise
- 19.15 Instruction for a Device Use
- Appendix 1. Package Dimensions
- Appendix 2. Functional Difference
- Register Index
- REVISION HISTORY

1. Overview
page 2
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0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
Item Specification
CPU Basic instructions 91 instructions
Minimun instruction
41.7 ns (f(BCLK) = 24MHZ
(3)
, VCC = 4.2 to 5.5 V) (M16C/26B)
execution time
50 ns (f(BCLK) = 20MHZ, VCC = 3.0 to 5.5 V)
(M16C/26A, M16C/26B, M16C/26T(T-ver.))
100 ns (f(BCLK) = 10MHZ, VCC = 2.7 to 5.5 V)
(M16C/26A , M16C/26B)
50 ns (f(BCLK) = 20MHZ, VCC = 4.2 to 5.5 V -40 to 105°C)
(M16C/26T(V-ver.))
62.5 ns (f(BCLK) = 16MHZ, VCC = 4.2 to 5.5 V -40 to 125°C)
(M16C/26T(V-ver.))
Operating mode Single-chip mode
Address space 1 Mbyte
Memory capacity ROM/RAM: See 1.4 Product Information
Peripheral I/O ports 39 I/O pins
Function Multifunction timers TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels
Three-phase motor control timer
Serial I/O 2 channels (UART, clock synchronous serial I/O)
1 channel
(UART, clock synchronous, I
2
C bus, or IEBus
(1)
)
A/D converter 10 bit A/D Converter : 1 circuit, 12 channels
DMAC 2 channels
CRC calcuration circuit
1 circuit (CRC-CCITT and CRC-16) with MSB/LSB selectable
Watchdog timer 15 bits x 1 channel (with prescaler)
Interrupts 20 internal and 8 external sources, 4 software sources,
Interrupt priority level: 7
Clock generation circuit 4 circuits
Main clock oscillation circuit(*), Sub-clock oscillation circuit(*)
On-chip oscillator, PLL frequency synthesizer
(*)Equipped with a built-in feedback resister.
Oscillation stop detection Main clock oscillation stop, re-oscillation detection function
Voltage detection circuit On-chip (M16C/26A, M16C/26B), not on-chip (M16C/26T)
Electrical Power supply voltage VCC = 4.2 to 5.5 V (f(BCLK) = 24 MHZ)
(3)
(M16C/26B)
Characteristics V
CC = 3.0 to 5.5 V (f(BCLK) = 20 MHZ) (M16C/26A, M16C/26B)
VCC = 2.7 to 5.5 V (f(BCLK) = 10 MHZ)
VCC = 3.0 to 5.5 V (M16C/26T(T-ver.))
VCC = 4.2 to 5.5 V (M16C/26T(V-ver.))
Power consumption 20 mA (Vcc = 5 V, f(BCLK) = 24 MHz) (M16C/26B)
16 mA (Vcc = 5 V, f(BCLK) = 20 MHz)
25 µA (f(XCIN) = 32 KHz on RAM)
3 µA (Vcc = 3 V, f(XCIN) = 32 KHz, in wait mode)
0.7 µA (Vcc = 3 V, in stop mode)
Flash Memory Programming /erasure 2.7 to 5.5 V (M16C/26A, M16C/26B)
Version voltage 3.0 to 5.5 V (M16C/26T(T-ver.)) 4.2 to 5.5 V (M16C/26T(V-ver.))
Programming /erasure
100 times (all area) or 1,000 times (block 0 to 3)
endurance
/ 10,000 times
(block A, block B)
(2)
Operating Ambient Temperature -20 to 85°C / -40 to 85°C
(2)
(M16C/26A , M16C/26B)
-40 to 85°C (M16C/26T(T-ver.))
-40 to 105°C / -40 to 125°C (M16C/26T(V-ver.))
Package 48-pin plastic molded QFP
NOTES:
1. IEBus is a trademark of NEC Electronics Corporation.
2. See Tables 1.7 to 1.10 Product Code for the program and erase endurance, and operating ambient temperature.
3. The PLL frequency synthesizer is used to run the M16C/26B at f(BCLK) = 24 MHz.
Table 1.1. M16C/26A Group(M16C/26A, M16C/26B, M16C/26T) Performance (48-Pin Package)
1.2 Performance Outline
Table 1.1 and 1.2 outline performance overview of the M16C/26A Group (M16C/26A, M16C/26B, M16C/
26T).