Datasheet
Table Of Contents
- Notes regarding these materials
- General Precautions in the Handling of MPU/MCU Products
- How to Use This Manual
- Table of Contents
- Quick Reference by Address B-
- 1. Overview
- 2. Central Processing Unit (CPU)
- 2.1 Data Registers (R0, R1, R2 and R3)
- 2.2 Address Registers (A0 and A1)
- 2.3 Frame Base Register (FB)
- 2.4 Interrupt Table Register (INTB)
- 2.5 Program Counter (PC)
- 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
- 2.7 Static Base Register (SB)
- 2.8 Flag Register (FLG)
- 2.8.1 Carry Flag (C Flag)
- 2.8.2 Debug Flag (D Flag)
- 2.8.3 Zero Flag (Z Flag)
- 2.8.4 Sign Flag (S Flag)
- 2.8.5 Register Bank Select Flag (B Flag)
- 2.8.6 Overflow Flag (O Flag)
- 2.8.7 Interrupt Enable Flag (I Flag)
- 2.8.8 Stack Pointer Select Flag (U Flag)
- 2.8.9 Processor Interrupt Priority Level (IPL)
- 2.8.10 Reserved Area
- 3. Memory
- 4. Special Function Registers (SFRs)
- 5. Reset
- 6. Processor Mode
- 7. Clock Generation Circuit
- 8. Protection
- 9. Interrupt
- 10. Watchdog Timer
- 11. DMAC
- 12. Timer
- 13. Serial I/O
- 14. A/D Converter
- 15. CRC Calculation Circuit
- 16. Programmable I/O Ports
- 16.1 Port Pi Direction Register (PDi Register, i = 1, 6 to 10)
- 16.2 Port Pi Register (Pi Register, i = 1, 6 to 10)
- 16.3 Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers)
- 16.4 Port Control Register
- 16.5 Pin Assignment Control register (PACR)
- 16.6 Digital Debounce function
- 17. Flash Memory Version
- 17.1 Flash Memory Performance
- 17.2 Memory Map
- 17.3 Functions To Prevent Flash Memory from Rewriting
- 17.4 CPU Rewrite Mode
- 17.5 Register Description
- 17.6 Precautions in CPU Rewrite Mode
- 17.6.1 Operation Speed
- 17.6.2 Prohibited Instructions
- 17.6.3 Interrupts
- 17.6.4 How to Access
- 17.6.5 Writing in the User ROM Space
- 17.6.6 DMA Transfer
- 17.6.7 Writing Command and Data
- 17.6.8 Wait Mode
- 17.6.9 Stop Mode
- 17.6.10 Low Power Consumption Mode and On-chip Oscillator-Low Power Consumption Mode
- 17.7 Software Commands
- 17.8 Status Register
- 17.9 Standard Serial I/O Mode
- 17.10 Parallel I/O Mode
- 18. Electrical Characteristics
- 19. Usage Notes
- 19.1 SFR
- 19.2 PLL Frequency Synthesizer
- 19.3 Power Control
- 19.4 Protect
- 19.5 Interrupts
- 19.6 DMAC
- 19.7 Timer
- 19.8 Serial I/O
- 19.9 A/D Converter
- 19.10 Programmable I/O Ports
- 19.11 Electric Characteristic Differences Between Mask ROM
- 19.12 Mask ROM Version
- 19.13 Flash Memory Version
- 19.13.1 Functions to Inhibit Rewriting Flash Memory
- 19.13.2 Stop mode
- 19.13.3 Wait mode
- 19.13.4 Low power dissipation mode, on-chip oscillator low power dissipation mode
- 19.13.5 Writing command and data
- 19.13.6 Program Command
- 19.13.7 Operation speed
- 19.13.8 Instructions prohibited in EW0 Mode
- 19.13.9 Interrupts
- 19.13.10 How to access
- 19.13.11 Writing in the user ROM area
- 19.13.12 DMA transfer
- 19.13.13 Regarding Programming/Erasure Times and Execution Time
- 19.13.14 Definition of Programming/Erasure Times
- 19.13.15 Flash Memory Version Electrical Characteristics 10,000 E/W cycle product
- 19.13.16 Boot Mode
- 19.14 Noise
- 19.15 Instruction for a Device Use
- Appendix 1. Package Dimensions
- Appendix 2. Functional Difference
- Register Index
- REVISION HISTORY

14. A/D Converter
page 187
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A/D control register 0 (1)
Symbol
Address
After reset
ADCON0
03D6
16
00000XXX
2
b7 b6 b5 b4 b3 b2 b1 b0
Analog Input Pin
Select Bit (2, 3)
CH0
Bit symbol Bit name Function
CH1
CH2
A/D Operation Mode
Select Bit 0 (3)
MD0
MD
1
Trigger Select Bit
TRG
ADST
A/D Conversion Start
Flag
0 : A/D conversion disabled
1 : A/D conversion started
Frequency Select Bit 0CKS0
RW
A/D control register 1 (1)
Symbol
Address
After reset
ADCON1
03D716
0016
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A/D Sweep Pin
Select Bit
SCAN0
SCAN1
MD
2
BITS
8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
VCUT
V
REF Connect Bit (2)
A/D Operation Mode
Select Bit 1
1 : V
REF connected
0
0
0 0 : One-shot mode or delayed trigger mode
0,1
b4 b3
1
Frequency Select Bit 1
CKS1
0 : Any mode other than repeat sweep
mode 1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
See Table 14.2 A/D Conversion
Frequency Select
Refer to Table 14.2 A/D Conversion
Frequency Select
(b7-b6)
0
NOTE:
1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D control register 2 (1)
Symbol
Address
After reset
ADCON2 03D416 0016
b7 b6 b5 b4 b3 b2 b1 b0
A/D Conversion Method
Select Bit
Bit symbol Bit name Function RW
SMP
Reserved Bit
Set to
“0”
0
A/D Input Group Select
Bit
0 0 : Select port P10 group (AN
i)
0 1 : Select port P9 group (AN
3i)
1 0 : Do not set
1 1 : Select port P9 group (AN
24)
b2 b1
Frequency Select Bit 2
CKS2
ADGSEL0
ADGSEL1
RW
RW
RW
RW
RW
(b3)
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
RW
TRG1
Trigger Select Bit 1
b2 b1 b0
0 0 0 : Select AN
0
0 0 1 : Select AN1
0 1 0 : Select AN2
0 1 1 : Select AN3
1 0 0 : Select AN
4
1 0 1 : Select AN5
1 1 0 : Select AN6
1 1 1 : Select AN
7
0 : Software trigger
1 : Hardware trigger (AD
TRG trigger)
Invalid in one-shot mode
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
0 : Without sample and hold
1 : With sample and hold
Set to "0" in one-shot mode
See Table 14.2 A/D Conversion
Frequency Select
0
NOTES:
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. AN
30 to AN32 and AN24 can be used in the same way as AN0 to AN7 . Use the ADGSEL1 to ADGSEL0 bits in the
ADCON2 register to select the desired pin.
3. After rewriting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using an another instruction.
NOTES:
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. If the VCUT bit is reset from “0” (V
REF unconnected) to “1” (VREF connected), wait for 1 µs or more before starting A/D
conversion.
Figure 14.1.1.2 ADCON0 to ADCON2 Registers in One-Shot Mode