Datasheet
Table Of Contents
- Notes regarding these materials
- General Precautions in the Handling of MPU/MCU Products
- How to Use This Manual
- Table of Contents
- Quick Reference by Address B-
- 1. Overview
- 2. Central Processing Unit (CPU)
- 2.1 Data Registers (R0, R1, R2 and R3)
- 2.2 Address Registers (A0 and A1)
- 2.3 Frame Base Register (FB)
- 2.4 Interrupt Table Register (INTB)
- 2.5 Program Counter (PC)
- 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
- 2.7 Static Base Register (SB)
- 2.8 Flag Register (FLG)
- 2.8.1 Carry Flag (C Flag)
- 2.8.2 Debug Flag (D Flag)
- 2.8.3 Zero Flag (Z Flag)
- 2.8.4 Sign Flag (S Flag)
- 2.8.5 Register Bank Select Flag (B Flag)
- 2.8.6 Overflow Flag (O Flag)
- 2.8.7 Interrupt Enable Flag (I Flag)
- 2.8.8 Stack Pointer Select Flag (U Flag)
- 2.8.9 Processor Interrupt Priority Level (IPL)
- 2.8.10 Reserved Area
- 3. Memory
- 4. Special Function Registers (SFRs)
- 5. Reset
- 6. Processor Mode
- 7. Clock Generation Circuit
- 8. Protection
- 9. Interrupt
- 10. Watchdog Timer
- 11. DMAC
- 12. Timer
- 13. Serial I/O
- 14. A/D Converter
- 15. CRC Calculation Circuit
- 16. Programmable I/O Ports
- 16.1 Port Pi Direction Register (PDi Register, i = 1, 6 to 10)
- 16.2 Port Pi Register (Pi Register, i = 1, 6 to 10)
- 16.3 Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers)
- 16.4 Port Control Register
- 16.5 Pin Assignment Control register (PACR)
- 16.6 Digital Debounce function
- 17. Flash Memory Version
- 17.1 Flash Memory Performance
- 17.2 Memory Map
- 17.3 Functions To Prevent Flash Memory from Rewriting
- 17.4 CPU Rewrite Mode
- 17.5 Register Description
- 17.6 Precautions in CPU Rewrite Mode
- 17.6.1 Operation Speed
- 17.6.2 Prohibited Instructions
- 17.6.3 Interrupts
- 17.6.4 How to Access
- 17.6.5 Writing in the User ROM Space
- 17.6.6 DMA Transfer
- 17.6.7 Writing Command and Data
- 17.6.8 Wait Mode
- 17.6.9 Stop Mode
- 17.6.10 Low Power Consumption Mode and On-chip Oscillator-Low Power Consumption Mode
- 17.7 Software Commands
- 17.8 Status Register
- 17.9 Standard Serial I/O Mode
- 17.10 Parallel I/O Mode
- 18. Electrical Characteristics
- 19. Usage Notes
- 19.1 SFR
- 19.2 PLL Frequency Synthesizer
- 19.3 Power Control
- 19.4 Protect
- 19.5 Interrupts
- 19.6 DMAC
- 19.7 Timer
- 19.8 Serial I/O
- 19.9 A/D Converter
- 19.10 Programmable I/O Ports
- 19.11 Electric Characteristic Differences Between Mask ROM
- 19.12 Mask ROM Version
- 19.13 Flash Memory Version
- 19.13.1 Functions to Inhibit Rewriting Flash Memory
- 19.13.2 Stop mode
- 19.13.3 Wait mode
- 19.13.4 Low power dissipation mode, on-chip oscillator low power dissipation mode
- 19.13.5 Writing command and data
- 19.13.6 Program Command
- 19.13.7 Operation speed
- 19.13.8 Instructions prohibited in EW0 Mode
- 19.13.9 Interrupts
- 19.13.10 How to access
- 19.13.11 Writing in the user ROM area
- 19.13.12 DMA transfer
- 19.13.13 Regarding Programming/Erasure Times and Execution Time
- 19.13.14 Definition of Programming/Erasure Times
- 19.13.15 Flash Memory Version Electrical Characteristics 10,000 E/W cycle product
- 19.13.16 Boot Mode
- 19.14 Noise
- 19.15 Instruction for a Device Use
- Appendix 1. Package Dimensions
- Appendix 2. Functional Difference
- Register Index
- REVISION HISTORY
14. A/D Converter
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Figure 14.4 ADSTAT0 Register and AD0 to AD7 Registers
A/D Register i (i=0 to 7)
Symbol Address After reset
AD0 03C116 to 03C016 Indeterminate
AD1 03C316 to 03C216 Indeterminate
AD2
03C516 to 03C416 Indeterminate
AD3
03C716 to 03C616 Indeterminate
AD4
03C916 to 03C816 Indeterminate
AD5
03CB16 to 03CA16 Indeterminate
AD6
03CD16 to 03CC16 Indeterminate
AD7
03CF16 to 03CE16 Indeterminate
Eight low-order bits of
A/D conversion result
Function
(b15)
b7b7 b0 b0
(b8)
When the BITS bit in the ADCON1
register is “1” (10-bit mode)
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
When read, its content is
indeterminate
RW
RO
RO
Two high-order bits of
A/D conversion result
When the BITS bit in the ADCON1
register is “0” (8-bit mode)
A/D conversion result
A/D conversion status register 0 (1)
Symbol
Address
After reset
ADSTAT0 03D316 0016
b7 b6 b5 b4 b3 b2 b1 b0
AN1 Trigger Status Flag
0 : AN1 trigger did not occur during
AN0 conversion
1 : AN1 trigger occured during AN0
conversion
Bit symbol Bit name Function RW
ADERR0
Conversion Termination
Flag
AN0 Conversion Status
Flag
ADSTT0
ADERR1
ADTCSF
RW
RO
RW
RO
RO
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b2
)
ADSTRT0
AN0 Conversion
Completion Status Flag
0 : Conversion not terminated
1 : Conversion terminated by
Timer B0 underflo
w
Delayed Trigger Sweep
Status Flag
0 : Sweep not in progress
1 : Sweep in progress
0 : AN0 conversion not in progress
1 : AN0 conversion in progress
ADSTT1
RW
0 : AN0 conversion not completed
1 : AN0 conversion completed
ADSTRT1
RW
AN1 Conversion Status
Flag
0 : AN1 conversion not in progress
1 : AN1 conversion in progress
AN1 Conversion
Completion Status Flag
0 : AN1 conversion not completed
1 : AN1 conversion completed
NOTE:
1. ADSTAT0 register is valid only when the DTE bit in the ADTRGCON register is set to “1”.