Datasheet

14. A/D Converter
page 183
923fo7002,51.beF00.2.veR
0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
A/D trigger control register
(1,2)
Symbol Address After reset
ADTRGCON 03D2 16 00 16
b7 b6 b5 b4 b3 b2 b1 b0
A/D Operation Mode
Select Bit 2
0 : Other than simultaneous sample sweep
mode or delayed trigger mode 0,1
1 : Simultaneous sample sweep mode or
delayed trigger mode 0,1
Bit symbol
Bit name Function
RW
SSE
A/D Operation Mode
Select Bit 3
HPTRG1
DTE
HPTRG0
RW
RW
RW
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b4)
0 : Other than delayed trigger mode 0,1
1 : Delayed trigger mode 0,1
AN1 Trigger Select Bit
AN0 Trigger Select Bit
Function varies with each operation mode
Function varies with each operation mode
NOTES:
1. If the ADTRGCON register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. Set “00
16 ” in this register in one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0 and repeat sweep
mode 1.
Figure 14.3 ADTRGCON Register
CKS2 CKS1 CKS0 Ø AD
000
001
010
100
101
110
111
Divided-by-4 of f AD
Divided-by-2 of f AD
f AD
Divided-by-12 of f AD
011
Divided-by-6 of f
AD
Divided-by-3 of f AD
Table 14.2 A/D Conversion Frequency Select
NOTE:
1. Set the φAD frequency to 10 MHz or less (12 MHz or less in M16C/26B). The φAD is selected with
combinations of the CKS0 bit in the ADCON0 register, CKS1 bit in the ADCON1 register, and the
CKS2 bit in the ADCON2 register.