Datasheet

14. A/D Converter
page 181
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0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
Figure 14.1 A/D Converter Block Diagram
=0002
=0012
=0102
=0112
=1002
=1012
=1102
=1112
AN 0
AN 1
AN 2
AN 3
AN 4
AN 5
AN 6
AN 7
AN 30
AN 31
AN 32
V ref
V IN
CH2 to CH0
Decoder
for channel
selection
A/D register 0(16)
Data bus low-order
V REF
AV SS
VCUT=0
VCUT=1
Data bus high-order
Port P10 group
Port P9 group
ADGSEL1 to ADGSEL0=012
ADGSEL1 to ADGSEL0=002
AN 24
ADGSEL1 to ADGSEL0=112
f AD
CKS0=1
CKS0=0
CKS1=1
CKS1=0
1/3
CKS2=0
CKS2=1
1/21/2
ø AD
A/D conversion rate
selection
(03C1 16 to 03C0 16 )
(03C3
16 to 03C2 16 )
(03C5
16 to 03C4 16 )
(03C7
16 to 03C6 16 )
(03C9
16 to 03C8 16 )
(03CB
16 to 03CA 16 )
(03CD
16 to 03CC 16 )
(03CF
16 to 03CE 16 )
Resistor ladder
Successive conversion register
ADCON0 register
(address 03D6
16)
ADCON1 register
(address 03D7
16)
Comparator 0
Addresses
Decoder
for A/D register
A/D register 1(16)
A/D register 2(16)
A/D register 3(16)
A/D register 4(16)
A/D register 5(16)
A/D register 6(16)
A/D register 7(16)
ADCON2 register
(address 03D4
16 )
Port P9 group
=0002
=0012
=0102
=1002
CH2 to CH0
CH2 to CH0
SSE = 1
CH2 to CH0=001
2
Comparator 1
ADGSEL1 to ADGSEL0=002
ADGSEL1 to ADGSEL0=012
V IN1
(1)
(1)
NOTE:
1. AN
32 and AN24 are available for only 48-pin package.