Datasheet

14. A/D Converter
page 180
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Item Performance
A/D Conversion Method Successive approximation (capacitive coupling amplifier)
Analog Input Voltage
(1)
0V to AVCC (VCC)
Operating Clock fAD
(2)
fAD/divided-by-2 or fAD/divided-by-3 or fAD/divided-by-4 or fAD/divided-by-6
or fAD/divided-by-12 or fAD
Resolution 8-bit or 10-bit (selectable)
Integral Nonlinearity Error When AVCC = VREF = 5V
• With 8-bit resolution: ±2LSB
• With 10-bit resolution: ±3LSB
When AVCC = VREF = 3.3V
• With 8-bit resolution: ±2LSB
• With 10-bit resolution: ±5LSB
Operating Modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, repeat
sweep mode 1, simultaneous sample sweep mode and delayed trigger mode 0,1
Analog Input Pins
(3)
8 pins (AN0 to AN7) + 3 pins (AN30 to AN32) + 1 pins (AN24) (48-pin package)
8 pins (AN0 to AN7) + 2 pins (AN30, AN31) (42-pin package)
Conversion Speed Per Pin • Without sample and hold function
8-bit resolution: 49 fAD cycles , 10-bit resolution: 59 fAD cycles
• With sample and hold function
8-bit resolution: 28 fAD cycles , 10-bit resolution: 33 fAD cycles
Table 14.1 A/D Converter Performance
NOTES:
1. Not dependent on use of sample and hold function.
2. Set the φAD frequency to 10 MHz or less. For M16C/26B, set it to 12 MHz or less.
Without sample-and-hold function, set the fAD frequency to 250kHZ or more.
With the sample and hold function, set the fAD frequency to 1MHZ or more.
14. A/D Converter
Note
P92 and P93 (AN32, AN24) are not available in the 42-pin package.
Do not use P92 and P93 (AN32, AN24) as analog input pins in the 42-pin package.
The microcomputer contains one A/D converter circuit based on 10-bit successive approximation method
configured with a capacitive-coupling amplifier. The analog inputs share the pins with P100 to P107 (AN0 to
___________
AN7), P90 to P93 (AN30 to AN32, AN24). Similarly, ADTRG input shares the pin with P15. Therefore, when
using these inputs, make sure the corresponding port direction bits are set to “0” (input mode).
When not using the A/D converter, set the VCUT bit to “0” (VREF unconnected), so that no current will flow
from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip.
The A/D conversion result is stored in the i bits in the A/D register for ANi, AN3i, and AN2i pins (i = 0 to 7).
Table 14.1 shows the A/D converter performance. Figure 14.1 shows the A/D converter block diagram
and Figures 14.2 to 14.4 show the A/D converter associated with registers.