Datasheet

13. Serial I/O
page 178
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0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
Figure 13.1.6.2 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply
pull-up.
Figure 13.1.6.2. SIM Interface Connection
Microcomputer
SIM card
TxD
2
RxD2
13.1.6.1 Parity Error Signal Output
The parity error signal is enabled by setting the U2ERE bit in the U2C1 register’ to “1”.
• When receiving
The parity error signal is output when a parity error is detected while receiving data. This is achieved
by pulling the TxD2 output low with the timing shown in Figure 13.1.6.1.1. If the R2RB register is read
while outputting a parity error signal, the PER bit is cleared to “0” and at the same time the TxD2 output
is returned high.
• When transmitting
A transmission-finished interrupt request is generated at the falling edge of the transfer clock pulse
that immediately follows the stop bit. Therefore, whether a parity signal has been returned can be
determined by reading the port that shares the RxD2 pin in a transmission-finished interrupt service
routine.
Figure 13.1.6.1.1. Parity Error Signal Output Timing
D0 D1 D2 D3 D4 D5 D6 D7 PSPST
(1)
Transfer
clock
RxD
2
TxD 2
U2C1 register
RI bit
“H”
“L”
“H”
“L”
“H”
“L”
“1”
“0”
This timing diagram applies to the case where the direct format is implemented.
NOTE:
1. The output of microcomputer is in the high-impedance state
(pulled up externally).
ST: Start bit
P: Even Parity
SP: Stop bit