Datasheet
Table Of Contents
- Notes regarding these materials
- General Precautions in the Handling of MPU/MCU Products
- How to Use This Manual
- Table of Contents
- Quick Reference by Address B-
- 1. Overview
- 2. Central Processing Unit (CPU)
- 2.1 Data Registers (R0, R1, R2 and R3)
- 2.2 Address Registers (A0 and A1)
- 2.3 Frame Base Register (FB)
- 2.4 Interrupt Table Register (INTB)
- 2.5 Program Counter (PC)
- 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
- 2.7 Static Base Register (SB)
- 2.8 Flag Register (FLG)
- 2.8.1 Carry Flag (C Flag)
- 2.8.2 Debug Flag (D Flag)
- 2.8.3 Zero Flag (Z Flag)
- 2.8.4 Sign Flag (S Flag)
- 2.8.5 Register Bank Select Flag (B Flag)
- 2.8.6 Overflow Flag (O Flag)
- 2.8.7 Interrupt Enable Flag (I Flag)
- 2.8.8 Stack Pointer Select Flag (U Flag)
- 2.8.9 Processor Interrupt Priority Level (IPL)
- 2.8.10 Reserved Area
- 3. Memory
- 4. Special Function Registers (SFRs)
- 5. Reset
- 6. Processor Mode
- 7. Clock Generation Circuit
- 8. Protection
- 9. Interrupt
- 10. Watchdog Timer
- 11. DMAC
- 12. Timer
- 13. Serial I/O
- 14. A/D Converter
- 15. CRC Calculation Circuit
- 16. Programmable I/O Ports
- 16.1 Port Pi Direction Register (PDi Register, i = 1, 6 to 10)
- 16.2 Port Pi Register (Pi Register, i = 1, 6 to 10)
- 16.3 Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers)
- 16.4 Port Control Register
- 16.5 Pin Assignment Control register (PACR)
- 16.6 Digital Debounce function
- 17. Flash Memory Version
- 17.1 Flash Memory Performance
- 17.2 Memory Map
- 17.3 Functions To Prevent Flash Memory from Rewriting
- 17.4 CPU Rewrite Mode
- 17.5 Register Description
- 17.6 Precautions in CPU Rewrite Mode
- 17.6.1 Operation Speed
- 17.6.2 Prohibited Instructions
- 17.6.3 Interrupts
- 17.6.4 How to Access
- 17.6.5 Writing in the User ROM Space
- 17.6.6 DMA Transfer
- 17.6.7 Writing Command and Data
- 17.6.8 Wait Mode
- 17.6.9 Stop Mode
- 17.6.10 Low Power Consumption Mode and On-chip Oscillator-Low Power Consumption Mode
- 17.7 Software Commands
- 17.8 Status Register
- 17.9 Standard Serial I/O Mode
- 17.10 Parallel I/O Mode
- 18. Electrical Characteristics
- 19. Usage Notes
- 19.1 SFR
- 19.2 PLL Frequency Synthesizer
- 19.3 Power Control
- 19.4 Protect
- 19.5 Interrupts
- 19.6 DMAC
- 19.7 Timer
- 19.8 Serial I/O
- 19.9 A/D Converter
- 19.10 Programmable I/O Ports
- 19.11 Electric Characteristic Differences Between Mask ROM
- 19.12 Mask ROM Version
- 19.13 Flash Memory Version
- 19.13.1 Functions to Inhibit Rewriting Flash Memory
- 19.13.2 Stop mode
- 19.13.3 Wait mode
- 19.13.4 Low power dissipation mode, on-chip oscillator low power dissipation mode
- 19.13.5 Writing command and data
- 19.13.6 Program Command
- 19.13.7 Operation speed
- 19.13.8 Instructions prohibited in EW0 Mode
- 19.13.9 Interrupts
- 19.13.10 How to access
- 19.13.11 Writing in the user ROM area
- 19.13.12 DMA transfer
- 19.13.13 Regarding Programming/Erasure Times and Execution Time
- 19.13.14 Definition of Programming/Erasure Times
- 19.13.15 Flash Memory Version Electrical Characteristics 10,000 E/W cycle product
- 19.13.16 Boot Mode
- 19.14 Noise
- 19.15 Instruction for a Device Use
- Appendix 1. Package Dimensions
- Appendix 2. Functional Difference
- Register Index
- REVISION HISTORY
13. Serial I/O
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Figure 13.1.3.2. Transfer to U2RB Register and Interrupt Timing
(4) When the IICM2 bit is set to "1" and the CKPH bit is set to "1"
(3) When the IICM2 bit is set to "1" (UART transmit or receive interrupt) and the CKPH bit is set to "0"
SDA2
SCL2
Receive interrupt
(DMA request)
Transmit interrupt
SDA2
SCL2
The above timing applies to the following setting :
• The CKDIR bit in the U2MR register is set to "1" (slave)
(1) When the IICM2 bit is set to "0" (ACK or NACK interrupt) and the CKPH bit is set to "0" (No clock delay)
D6 D5 D4 D3 D2 D1 D8 (ACK or NACK)D7
SDA2
SCL2
D0
ACK interrupt (DMA
request) or NACK interrupt
(2) When the IICM2 bit is set to "0" and the CKPH bit is set to "1" (clock delay)
SDA2
SCL2
1st
bit
2nd
bit
3rd
bit
4th
bit
5th
bit
6th
bit
7th
bit
8th
bit
9th
bit
b15
•••
b9 b8 b7 b0
D
8
Contents of the U2RB register
b15
•••
b9 b8 b7 b0
b15
•••
b9 b8 b7 b0
b15
•••
b9 b8 b7 b0 b15
•••
b9 b8 b7 b0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D6 D5 D4 D3 D2 D1D7 D0
ACK interrupt (DMA
request) or NACK interrupt
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D6 D5 D4 D3 D2 D1D7 D0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D6 D5 D4 D3 D2 D1D7 D0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D8 (ACK or NACK)
1st
bit
2nd
bit
3rd
bit
4th
bit
5th
bit
6th
bit
7th
bit
8th
bit
9th
bit
D8 (ACK or NACK)
1st
bit
2nd
bit
3rd
bit
4th
bit
5th
bit
6th
bit
7th
bit
8th
bit
9th
bit
D8 (ACK or NACK)
1st
bit
2nd
bit
3rd
bit
4th
bit
5th
bit
6th
bit
7th
bit
8th
bit
9th
bit
Data is transferred to the U2RB register
Data is transferred to the U2RB register
Data is transferred to the U2RB register
Receive interrupt
(DMA request)
Transmit interrupt
Data is transferred to the U2RB register
Data is transferred to the U2RB register
Contents of the U2RB register
Contents of the U2RB register
Contents of the U2RB register
Contents of the U2RB register