Datasheet
Table Of Contents
- Notes regarding these materials
- General Precautions in the Handling of MPU/MCU Products
- How to Use This Manual
- Table of Contents
- Quick Reference by Address B-
- 1. Overview
- 2. Central Processing Unit (CPU)
- 2.1 Data Registers (R0, R1, R2 and R3)
- 2.2 Address Registers (A0 and A1)
- 2.3 Frame Base Register (FB)
- 2.4 Interrupt Table Register (INTB)
- 2.5 Program Counter (PC)
- 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
- 2.7 Static Base Register (SB)
- 2.8 Flag Register (FLG)
- 2.8.1 Carry Flag (C Flag)
- 2.8.2 Debug Flag (D Flag)
- 2.8.3 Zero Flag (Z Flag)
- 2.8.4 Sign Flag (S Flag)
- 2.8.5 Register Bank Select Flag (B Flag)
- 2.8.6 Overflow Flag (O Flag)
- 2.8.7 Interrupt Enable Flag (I Flag)
- 2.8.8 Stack Pointer Select Flag (U Flag)
- 2.8.9 Processor Interrupt Priority Level (IPL)
- 2.8.10 Reserved Area
- 3. Memory
- 4. Special Function Registers (SFRs)
- 5. Reset
- 6. Processor Mode
- 7. Clock Generation Circuit
- 8. Protection
- 9. Interrupt
- 10. Watchdog Timer
- 11. DMAC
- 12. Timer
- 13. Serial I/O
- 14. A/D Converter
- 15. CRC Calculation Circuit
- 16. Programmable I/O Ports
- 16.1 Port Pi Direction Register (PDi Register, i = 1, 6 to 10)
- 16.2 Port Pi Register (Pi Register, i = 1, 6 to 10)
- 16.3 Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers)
- 16.4 Port Control Register
- 16.5 Pin Assignment Control register (PACR)
- 16.6 Digital Debounce function
- 17. Flash Memory Version
- 17.1 Flash Memory Performance
- 17.2 Memory Map
- 17.3 Functions To Prevent Flash Memory from Rewriting
- 17.4 CPU Rewrite Mode
- 17.5 Register Description
- 17.6 Precautions in CPU Rewrite Mode
- 17.6.1 Operation Speed
- 17.6.2 Prohibited Instructions
- 17.6.3 Interrupts
- 17.6.4 How to Access
- 17.6.5 Writing in the User ROM Space
- 17.6.6 DMA Transfer
- 17.6.7 Writing Command and Data
- 17.6.8 Wait Mode
- 17.6.9 Stop Mode
- 17.6.10 Low Power Consumption Mode and On-chip Oscillator-Low Power Consumption Mode
- 17.7 Software Commands
- 17.8 Status Register
- 17.9 Standard Serial I/O Mode
- 17.10 Parallel I/O Mode
- 18. Electrical Characteristics
- 19. Usage Notes
- 19.1 SFR
- 19.2 PLL Frequency Synthesizer
- 19.3 Power Control
- 19.4 Protect
- 19.5 Interrupts
- 19.6 DMAC
- 19.7 Timer
- 19.8 Serial I/O
- 19.9 A/D Converter
- 19.10 Programmable I/O Ports
- 19.11 Electric Characteristic Differences Between Mask ROM
- 19.12 Mask ROM Version
- 19.13 Flash Memory Version
- 19.13.1 Functions to Inhibit Rewriting Flash Memory
- 19.13.2 Stop mode
- 19.13.3 Wait mode
- 19.13.4 Low power dissipation mode, on-chip oscillator low power dissipation mode
- 19.13.5 Writing command and data
- 19.13.6 Program Command
- 19.13.7 Operation speed
- 19.13.8 Instructions prohibited in EW0 Mode
- 19.13.9 Interrupts
- 19.13.10 How to access
- 19.13.11 Writing in the user ROM area
- 19.13.12 DMA transfer
- 19.13.13 Regarding Programming/Erasure Times and Execution Time
- 19.13.14 Definition of Programming/Erasure Times
- 19.13.15 Flash Memory Version Electrical Characteristics 10,000 E/W cycle product
- 19.13.16 Boot Mode
- 19.14 Noise
- 19.15 Instruction for a Device Use
- Appendix 1. Package Dimensions
- Appendix 2. Functional Difference
- Register Index
- REVISION HISTORY
B-2
Quick Reference by Address
Flash memory control register 0 FMR0
Flash memory control register 1 FMR1
Flash memory control register 4 FMR4
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
2. This register is included in the flash memory version.
0080
16
0081
16
0082
16
0083
16
0084
16
0085
16
0086
16
01B0
16
01B1
16
01B2
16
01B3
16
01B4
16
01B5
16
01B6
16
01B7
16
01B8
16
01B9
16
01BA
16
01BB
16
01BC
16
01BD
16
01BE
16
01BF
16
0250
16
0251
16
0252
16
0253
16
0254
16
0255
16
0256
16
0257
16
0258
16
0259
16
025A
16
025B
16
025C
16
025D
16
025E
16
025F
16
02E0
16
02E1
16
02E2
16
02E3
16
02E4
16
02E5
16
02E6
16
02E7
16
02E8
16
02E9
16
033D
16
033E
16
033F
16
Peripheral clock select register PCLKR
241
241
43
(2)
(2)
Address
Register Symbol Page
(2)
242
Pin assignment control register PACR
On-chip oscillator control register ROCR
139, 226
41
P1
7
digital debounce register P17DDR
NMI digital debounce register NDDR
227
227
Three phase protect control register TPRC
0340
16
0341
16
0342
16
0343
16
0344
16
0345
16
0346
16
0347
16
0348
16
0349
16
034A
16
034B
16
034C
16
034D
16
034E
16
034F
16
0350
16
0351
16
0352
16
0353
16
0354
16
0355
16
0356
16
0357
16
0358
16
0359
16
035A
16
035B
16
035C
16
035D
16
035E
16
035F
16
0360
16
0361
16
0362
16
0363
16
0364
16
0365
16
0366
16
0367
16
0368
16
0369
16
036A
16
036B
16
036C
16
036D
16
036E
16
036F
16
0370
16
0371
16
0372
16
0373
16
0374
16
0375
16
0376
16
0377
16
0378
16
0379
16
037A
16
037B
16
037C
16
037D
16
037E
16
037F
16
Timer A1-1 register TA11
Timer A2-1 register TA21
Dead time timer DTT
Timer B2 interrupt occurrence frequency set counter
ICTB2
Three-phase PWM control register 0 INVC0
Three-phase PWM control register 1 INVC1
Three-phase output buffer register 0 IDB0
Three-phase output buffer register 1 IDB1
Interrupt request cause select register
IFSR
UART2 special mode register U2SMR
UART2 receive buffer register
U2RB
UART2 transmit buffer register
U2TB
UART2 transmit/receive control register 0
U2C0
UART2 transmit/receive mode register
U2MR
UART2 transmit/receive control register 1
U2C1
UART2 bit rate generator
U2BRG
Timer A4-1 register TA41
UART2 special mode register 2 U2SMR2
UART2 special mode register 3 U2SMR3
UART2 special mode register 4 U2SMR4
122
122
122
119
120
121
121
121
122
141
141
140
140
137
136
136
138
139
136
68, 76
Address
Register Symbol Page
Position-data-retain function contol register
PDRF
129
Port function contol register PFCR
Interrupt request cause select register 2
IFSR2A
68
131
131