Datasheet

13. Serial I/O
page 153
923fo7002,51.beF00.2.veR
0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
Figure 13.1.2.1. Typical transmit timing in UART mode (UART0, UART1)
Start
bit
Parity
bit
TxDi
CTSi
“1”
“0”
“1”
“L”
“H”
“0”
“1”
Tc = 16 (n + 1) / fj or 16 (n + 1) / f EXT
fj : frequency of UiBRG count source (f 1SIO , f 2SIO , f 8SIO , f 32SIO )
f
EXT : frequency of UiBRG count source (external clock)
n : value set to UiBRG
i: 0 to 2
“0”
“1”
TxDi
“0”
“1”
“0”
“1”
“0”
“1”
Transfer clock
Tc
“0”
“1”
Tc
Transfer clock
D0
D1
D2
D3
D4
D5
D6
D7
ST
P
D0
D1
D2
D3
D4
D5
D6
D7SP
ST
P
SP
D
0
D1
ST
Stop
bit
Start
bit
The transfer clock stops momentarily as CTSi is “H” when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTSi changes to “L”.
D0
D1
D2
D3
D4
D5
D6
D7
ST
SP
D
8
D0
D1
D2
D3
D4
D5
D6
D7
ST
D
8
D0
D1
ST
SPSP
Stop
bit
Stop
bit
“0”
SP
Stopped pulsing
because the TE bit
= “0”
Write data to the UiTB register
UiC1 register
TE bit
UiC1 register
TI bit
UiC0 register
TXEPT bit
SiTIC register
IR bit
Transferred from UiTB register to UARTi transmit register
The above timing diagram applies to the case where the register bits are set
as follows:
• Set the PRYE bit in the UiMR register to "1" (parity enabled)
• Set the STPS bit in the UiMR register to "0" (1 stop bit)
• Set the CRD bit in the UiC0 register to "0" (CTS/RTS enabled),
the CRS bit to "0" (CTS selected)
• Set the UiIRS bit to "1" (an interrupt request occurs when transmit completed):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
UiC1 register
TE bit
UiC1 register
TI bit
UiC0 register
TXEPT bit
SiTIC register
IR bit
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
Write data to the UiTB register
Transferred from UiTB register to UARTi
transmit register
Tc = 16 (n + 1) / fj or 16 (n + 1) / f
EXT
fj : frequency of UiBRG count source (f 1SIO , f 2SIO , f 8SIO , f 32SIO )
f
EXT : frequency of UiBRG count source (external clock)
n : value set to UiBRG
i: 0 to 2
The above timing diagram applies to the case where the register bits are set
as follows:
• Set the PRYE bit in the UiMR register to "0" (parity disabled)
• Set the STPS bit in the UiMR register to "1" (2 stop bits)
• Set the CRD bit in the UiC0 register to "1"(CTS/RTS disabled)
• Set the UiIRS bit to "0" (an interrupt request occurs when transmit buffer
becomes empty):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)