Datasheet
Table Of Contents
- Notes regarding these materials
- General Precautions in the Handling of MPU/MCU Products
- How to Use This Manual
- Table of Contents
- Quick Reference by Address B-
- 1. Overview
- 2. Central Processing Unit (CPU)
- 2.1 Data Registers (R0, R1, R2 and R3)
- 2.2 Address Registers (A0 and A1)
- 2.3 Frame Base Register (FB)
- 2.4 Interrupt Table Register (INTB)
- 2.5 Program Counter (PC)
- 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
- 2.7 Static Base Register (SB)
- 2.8 Flag Register (FLG)
- 2.8.1 Carry Flag (C Flag)
- 2.8.2 Debug Flag (D Flag)
- 2.8.3 Zero Flag (Z Flag)
- 2.8.4 Sign Flag (S Flag)
- 2.8.5 Register Bank Select Flag (B Flag)
- 2.8.6 Overflow Flag (O Flag)
- 2.8.7 Interrupt Enable Flag (I Flag)
- 2.8.8 Stack Pointer Select Flag (U Flag)
- 2.8.9 Processor Interrupt Priority Level (IPL)
- 2.8.10 Reserved Area
- 3. Memory
- 4. Special Function Registers (SFRs)
- 5. Reset
- 6. Processor Mode
- 7. Clock Generation Circuit
- 8. Protection
- 9. Interrupt
- 10. Watchdog Timer
- 11. DMAC
- 12. Timer
- 13. Serial I/O
- 14. A/D Converter
- 15. CRC Calculation Circuit
- 16. Programmable I/O Ports
- 16.1 Port Pi Direction Register (PDi Register, i = 1, 6 to 10)
- 16.2 Port Pi Register (Pi Register, i = 1, 6 to 10)
- 16.3 Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers)
- 16.4 Port Control Register
- 16.5 Pin Assignment Control register (PACR)
- 16.6 Digital Debounce function
- 17. Flash Memory Version
- 17.1 Flash Memory Performance
- 17.2 Memory Map
- 17.3 Functions To Prevent Flash Memory from Rewriting
- 17.4 CPU Rewrite Mode
- 17.5 Register Description
- 17.6 Precautions in CPU Rewrite Mode
- 17.6.1 Operation Speed
- 17.6.2 Prohibited Instructions
- 17.6.3 Interrupts
- 17.6.4 How to Access
- 17.6.5 Writing in the User ROM Space
- 17.6.6 DMA Transfer
- 17.6.7 Writing Command and Data
- 17.6.8 Wait Mode
- 17.6.9 Stop Mode
- 17.6.10 Low Power Consumption Mode and On-chip Oscillator-Low Power Consumption Mode
- 17.7 Software Commands
- 17.8 Status Register
- 17.9 Standard Serial I/O Mode
- 17.10 Parallel I/O Mode
- 18. Electrical Characteristics
- 19. Usage Notes
- 19.1 SFR
- 19.2 PLL Frequency Synthesizer
- 19.3 Power Control
- 19.4 Protect
- 19.5 Interrupts
- 19.6 DMAC
- 19.7 Timer
- 19.8 Serial I/O
- 19.9 A/D Converter
- 19.10 Programmable I/O Ports
- 19.11 Electric Characteristic Differences Between Mask ROM
- 19.12 Mask ROM Version
- 19.13 Flash Memory Version
- 19.13.1 Functions to Inhibit Rewriting Flash Memory
- 19.13.2 Stop mode
- 19.13.3 Wait mode
- 19.13.4 Low power dissipation mode, on-chip oscillator low power dissipation mode
- 19.13.5 Writing command and data
- 19.13.6 Program Command
- 19.13.7 Operation speed
- 19.13.8 Instructions prohibited in EW0 Mode
- 19.13.9 Interrupts
- 19.13.10 How to access
- 19.13.11 Writing in the user ROM area
- 19.13.12 DMA transfer
- 19.13.13 Regarding Programming/Erasure Times and Execution Time
- 19.13.14 Definition of Programming/Erasure Times
- 19.13.15 Flash Memory Version Electrical Characteristics 10,000 E/W cycle product
- 19.13.16 Boot Mode
- 19.14 Noise
- 19.15 Instruction for a Device Use
- Appendix 1. Package Dimensions
- Appendix 2. Functional Difference
- Register Index
- REVISION HISTORY
13. Serial I/O
page 152
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Table 13.1.2.3 lists the functions of the input/output pins during UART mode. Table 13.1.2.4 lists the P64
pin functions during UART mode. Note that for a period from when the UARTi operation mode is selected
to when transfer starts, the TxDi pin outputs an “H”. (If the N-channel open-drain output is selected, this
pin is in a high-impedance state.)
Table 13.1.2.3. I/O Pin Functions in UART mode
(1)
Pin name Function Method of selection
TxDi (i = 0 to 2)
(P6
3, P67, P70)
Serial data output
Serial data input
Input/output port
Transfer clock input
Input/output port
(Outputs "H" when performing reception only)
RxDi
(P6
2, P66, P71)
CLKi
(P6
1, P65, P72)
Set the CKDIR bit in the UiMR register to "0"
Set the CKDIR bit in the UiMR register to "1"
Set the PD6_1 bit and PD6_5 bit in the PD6 register to "0", PD7_2 bit in the PD7
register to "0"
PD6_2 bit, PD6_6 bit in the PD6 register and the PD7_1 bit in the PD7 register
(Can be used as an input port when performing transmission only)
Set the CRD bit in the UiC0 register to "0"
Set the CRS bit in the UiC0 register to "0"
Set the PD6_0 bit and PD6_4 bit in the PD6 register to "0", the PD7_3 bit in the
PD7 register "0"
Set the CRD bit in the UiC0 register to "0"
Set the CRS bit in the UiC0 register to "1"
Set the CRD bit in the UiC0 register "1"
CTS input
RTS output
CTSi/RTSi
(P6
0, P64, P73)
NOTE:
1. When the U1MAP bit in PACR register is set to “1” (P7
3 to P70), UART1 pin is assgined to P73 to P70.
Table 13.1.2.4. P64 Pin Functions in UART mode
(1)
Pin function Bit set value
U1C0 register
UCON register
PD6 register
CRD
CRS
RCSP
CLKMD1
PD6_4
P6
4
1 0 0 Input: 0, Output: 1
CTS
1 0000
RTS
1 10 0
CTS0
(2)
0
0
0
00
10
NOTES:
1. When the U1MAP bit in PACR register is “1” (P7
3 to P70), this table lists the P70 functions.
2. In addition to this, set the CRD bit in the U0C0 register to “0” (CTS
0/RTS0 enabled) and the CRS bit in the U0C0
register to “1” (RTS
0 selected).