Datasheet

13. Serial I/O
page 141
923fo7002,51.beF00.2.veR
0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
UART2 special mode register 3
Symbol Address After reset
U2SMR3 0375
16 000X0X0X 2
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol
Function
DL2
SDA digital delay
setup bit
(1, 2)
DL0
DL1
0 0 0 : Without delay
0 0 1 : 1 to 2 cycle(s) of UiBRG count source
0 1 0 : 2 to 3 cycles of UiBRG count source
0 1 1 : 3 to 4 cycles of UiBRG count source
1 0 0 : 4 to 5 cycles of UiBRG count source
1 0 1 : 5 to 6 cycles of UiBRG count source
1 1 0 : 6 to 7 cycles of UiBRG count source
1 1 1 : 7 to 8 cycles of UiBRG count source
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
b7 b6 b5
0 : Without clock delay
1 : With clock delay
Clock phase set bit
0 : CLKi is CMOS output
1 : CLKi is N-channel open drain output
Clock output select bit
CKPH
NODC
RW
RW
RW
RW
RW
RW
(b0)
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
(b2)
(b4)
NOTES:
1. The DL2 to DL0 bits are used to generate a delay in SDA2 output by digital means during I
2
C bus mode. In other than
I
2
C bus mode, set these bits to “000 2 ” (no delay).
2. The amount of delay varies with the load on SCL2 and SDA2 pins. Also, when using an external clock, the amount of
delay increases by about 100 ns.
Figure 13.1.9. U2SMR3 register and U2SMR4 register
UART2 Special Mode Register 4
Symbol Address After Reset
U2SMR4 0374
16 0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit NameBit Symbol
RW
Function
ACKC
SCLHI
SWC9
ACK data bit
STAREQ
RSTAREQ
STPREQ
ACKD
0: Disabled
1: Enabled
0: ACK
1: NACK
0: Serial I/O data output
1: ACK data output
NOTE:
1. Set to “0” when each condition is generated.
STSPSEL
SCL2 wait bit 3
RW
RW
RW
RW
RW
RW
RW
RW
Start condition
generate bit
(1)
Restart condition
generate bit
(1)
Stop condition
ACK data output
SCL
2 output stop
SCL2, SDA2 output
0: Clear
1: Start
0: Clear
1: Start
0: Clear
1: Start
0: Start and stop conditions not output
1: Start and stop conditions output
0: SCL2 “L” hold disabled
1: SCL
2 “L” hold enabled