Datasheet

13. Serial I/O
page 140
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Figure 13.1.8. U2SMR register and U2SMR2 register
UART2 Special Mode Register
Symbol Address After Reset
U2SMR 0377
16 X00000002
b7 b6 b5 b4 b3 b2 b1 b0
Bit Name
Bit
Symbol
Function
ABSCS
ACSE
SSS
I
2
C bus mode select bit
Bus busy flag
0 : STOP condition detected
1 : START condition detected (busy)
Bus collision detect
sampling clock select bit
Arbitration lost detecting
flag control bit
0 : Other than I
2
C bus mode
1 : I
2
C bus mode
0 : Update per bit
1 :
Update per byte
IICM
ABC
BBS
0 : Not synchronized to R
XDi
1 : Synchronized to R
XDi
(2)
Set to “0”
Transmit start condition
select bit
0 : Rising edge of transfer clock
1 : Underflow signal of timer A0
Auto clear function
select bit of transmit
enable bit
0 : No auto clear function
1 : Auto clear at occurrence of bus collision
NOTES:
1: The BBS bit is set to “0” by writing “0" by program. (Writing “1” has no effect).
2: When a transfer begins, the SSS bit is set to “0” (Not synchronized to R
XDi).
(1)
Nothing is assigned. When write, set “0”.
When read, its content is indeterminate.
RW
RW
RW
RW
RW
RW
RW
RW
(b7)
0
(b3)
Reserved bit
UART2 Special Mode Register 2
Symbol Address After Reset
U2SMR2 0376
16 X0000000 2
b7 b6 b5 b4 b3 b2 b1 b0
Bit Name
Bit
Symbol
RWFunction
STAC
SWC2
SDHI
I C bus mode select bit 2
SCL
2 wait output bit 0 : Disabled
1 : Enabled
SDA
2 output stop bit
UART initialization bit
Clock-synchronous bit
Refer to Table 13.12
0 : Disabled
1 : Enabled
IICM2
CSC
SWC
ALS 0 : Disabled
1 : Enabled
SDA
2 output disable bit
SCL
2 wait output bit 2
0: Enabled
1: Disabled (high impedance)
0 : Disabled
1 : Enabled
0: Transfer clock
1: “L” output
2
Nothing is assigned. When write, set “0”.
When read, its content is indeterminate.
RW
RW
RW
RW
RW
RW
RW
(b7)