Datasheet
Table Of Contents
- Notes regarding these materials
- General Precautions in the Handling of MPU/MCU Products
- How to Use This Manual
- Table of Contents
- Quick Reference by Address B-
- 1. Overview
- 2. Central Processing Unit (CPU)
- 2.1 Data Registers (R0, R1, R2 and R3)
- 2.2 Address Registers (A0 and A1)
- 2.3 Frame Base Register (FB)
- 2.4 Interrupt Table Register (INTB)
- 2.5 Program Counter (PC)
- 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
- 2.7 Static Base Register (SB)
- 2.8 Flag Register (FLG)
- 2.8.1 Carry Flag (C Flag)
- 2.8.2 Debug Flag (D Flag)
- 2.8.3 Zero Flag (Z Flag)
- 2.8.4 Sign Flag (S Flag)
- 2.8.5 Register Bank Select Flag (B Flag)
- 2.8.6 Overflow Flag (O Flag)
- 2.8.7 Interrupt Enable Flag (I Flag)
- 2.8.8 Stack Pointer Select Flag (U Flag)
- 2.8.9 Processor Interrupt Priority Level (IPL)
- 2.8.10 Reserved Area
- 3. Memory
- 4. Special Function Registers (SFRs)
- 5. Reset
- 6. Processor Mode
- 7. Clock Generation Circuit
- 8. Protection
- 9. Interrupt
- 10. Watchdog Timer
- 11. DMAC
- 12. Timer
- 13. Serial I/O
- 14. A/D Converter
- 15. CRC Calculation Circuit
- 16. Programmable I/O Ports
- 16.1 Port Pi Direction Register (PDi Register, i = 1, 6 to 10)
- 16.2 Port Pi Register (Pi Register, i = 1, 6 to 10)
- 16.3 Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers)
- 16.4 Port Control Register
- 16.5 Pin Assignment Control register (PACR)
- 16.6 Digital Debounce function
- 17. Flash Memory Version
- 17.1 Flash Memory Performance
- 17.2 Memory Map
- 17.3 Functions To Prevent Flash Memory from Rewriting
- 17.4 CPU Rewrite Mode
- 17.5 Register Description
- 17.6 Precautions in CPU Rewrite Mode
- 17.6.1 Operation Speed
- 17.6.2 Prohibited Instructions
- 17.6.3 Interrupts
- 17.6.4 How to Access
- 17.6.5 Writing in the User ROM Space
- 17.6.6 DMA Transfer
- 17.6.7 Writing Command and Data
- 17.6.8 Wait Mode
- 17.6.9 Stop Mode
- 17.6.10 Low Power Consumption Mode and On-chip Oscillator-Low Power Consumption Mode
- 17.7 Software Commands
- 17.8 Status Register
- 17.9 Standard Serial I/O Mode
- 17.10 Parallel I/O Mode
- 18. Electrical Characteristics
- 19. Usage Notes
- 19.1 SFR
- 19.2 PLL Frequency Synthesizer
- 19.3 Power Control
- 19.4 Protect
- 19.5 Interrupts
- 19.6 DMAC
- 19.7 Timer
- 19.8 Serial I/O
- 19.9 A/D Converter
- 19.10 Programmable I/O Ports
- 19.11 Electric Characteristic Differences Between Mask ROM
- 19.12 Mask ROM Version
- 19.13 Flash Memory Version
- 19.13.1 Functions to Inhibit Rewriting Flash Memory
- 19.13.2 Stop mode
- 19.13.3 Wait mode
- 19.13.4 Low power dissipation mode, on-chip oscillator low power dissipation mode
- 19.13.5 Writing command and data
- 19.13.6 Program Command
- 19.13.7 Operation speed
- 19.13.8 Instructions prohibited in EW0 Mode
- 19.13.9 Interrupts
- 19.13.10 How to access
- 19.13.11 Writing in the user ROM area
- 19.13.12 DMA transfer
- 19.13.13 Regarding Programming/Erasure Times and Execution Time
- 19.13.14 Definition of Programming/Erasure Times
- 19.13.15 Flash Memory Version Electrical Characteristics 10,000 E/W cycle product
- 19.13.16 Boot Mode
- 19.14 Noise
- 19.15 Instruction for a Device Use
- Appendix 1. Package Dimensions
- Appendix 2. Functional Difference
- Register Index
- REVISION HISTORY
13. Serial I/O
page 133
923fo7002,51.beF00.2.veR
0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is selected)
Clock source selection
Internal
External
CTS/RTS disabled
CTS/RTS selected
RxD
0
1 / (n
0
+1)
1/16
1/16
1/2
U0BRG
registe
r
CLK
0
CTS
0
/ RTS
0
f
1SIO or
f
2SIO
f
8SIO
f
32SIO
V
CC
RTS
0
CTS
0
TxD
0
(UART0)
CLK1 to CLK0
00
2
01
2
10
2
CKDIR=0
CKDIR=1
CKPOL
CKDIR=0
CKDIR=
1
CRS=1
CRS=0
CRD=0
CRD=1
RCSP=0
RCSP=1
V
CC
CRD=0
CRD=1
UART reception
Clock synchronous
type
UART transmission
Clock synchronous
type
Clock synchronous type
(when internal clock is selected)
Receive
clock
Transmit
clock
Reception
control circuit
Transmission control
circuit
Transmit/
receive
unit
CLK
polarity
reversing
circuit
CTS/RTS disabled
CTS
0
from UART1
UART reception
Clock synchronous
type
RxD
1
TxD
1
(UART1)
1 / (n
1
+1)
1/16
1/16
1/2
U1BRG
register
CLK
1
f
1SIO or
f
2SIO
f
8SIO
f
32SIO
CLK1 to CLK0
00
2
01
2
10
2
CKDIR=0
CKDIR=1
CKPOL
CKDIR=0
CKDIR=
1
V
CC
CRD=0
CRD=1
CLKMD0=0
CLKMD1=0
CRS=1
CRS=0
RCSP=0
RCSP=1
CLKMD0=1
CLKMD1=1
Clock source selection
Internal
External
UART transmission
Clock synchronous
type
Clock synchronous type
(when internal clock is selected)
Receive
clock
Transmit
clock
Reception
control circuit
Transmission
control circuit
Transmit/
receive
unit
Clock synchronous type
(when external clock is selected)
Clock synchronous type
(when internal clock is selected)
CLK
polarity
reversing
circuit
RTS1
CTS1
Clock output
pin select
CTS/RTS disable
d
CTS/RTS disable
d
CTS/RTS selecte
d
CTS
0
from UART0
CTS
1
/ RTS
1
/
CTS
0
/ CLKS
1
i = 0 to 2
n
i
: Values set to the UiBRG register
SMD2 to SMD0, CKDIR: Bits in the UiMR
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in the UiC0 registers
CLKMD0, CLKMD1, RCSP: Bits in the UCON register
RxD
2
CLK
2
CTS
2
/ RTS
2
RTS
2
CTS
2
TxD
2
(UART2)
1 / (n
2
+1)
1/16
1/16
1/2
U2BRG
registe
r
f
1SIO or
f
2SIO
f
8SIO
f
32SIO
CLK1 to CLK0
00
2
01
2
10
2
CKDIR=0
CKDIR=1
CKPOL
CKDIR=0
CKDIR=
1
CRS=1
CRS=0
V
CC
CRD=0
CRD=1
Reception
control circuit
Transmission
control circuit
UART reception
Clock synchronous
type
UART transmission
Clock synchronous
type
Clock synchronous type
(when internal clock is selected)
Receive
clock
Transmit
clock
RxD polarity
reversing circuit
Internal
External
Clock source selection
TxD
polarity
reversing
circuit
Transmit/
receive
unit
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is selected)
CLK
polarity
reversing
circuit
CTS/RTS disabled
CTS/RTS disabled
CTS/RTS
selecte
d
Main clock, PLL clock,
or on-chip oscillator clock
1/2
1/8
1/4
f
1SIO
f
2SIO
f
8SIO
f
32SIO
f
1SIO or
f
2SIO
PCLK1=1
PCLK1=0
SMD2 to SMD0
SMD2 to SMD0
SMD2 to SMD0
Figure 13.1.1. Block diagram of UARTi (i = 0 to 2)