Datasheet
Table Of Contents
- Notes regarding these materials
- General Precautions in the Handling of MPU/MCU Products
- How to Use This Manual
- Table of Contents
- Quick Reference by Address B-
- 1. Overview
- 2. Central Processing Unit (CPU)
- 2.1 Data Registers (R0, R1, R2 and R3)
- 2.2 Address Registers (A0 and A1)
- 2.3 Frame Base Register (FB)
- 2.4 Interrupt Table Register (INTB)
- 2.5 Program Counter (PC)
- 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
- 2.7 Static Base Register (SB)
- 2.8 Flag Register (FLG)
- 2.8.1 Carry Flag (C Flag)
- 2.8.2 Debug Flag (D Flag)
- 2.8.3 Zero Flag (Z Flag)
- 2.8.4 Sign Flag (S Flag)
- 2.8.5 Register Bank Select Flag (B Flag)
- 2.8.6 Overflow Flag (O Flag)
- 2.8.7 Interrupt Enable Flag (I Flag)
- 2.8.8 Stack Pointer Select Flag (U Flag)
- 2.8.9 Processor Interrupt Priority Level (IPL)
- 2.8.10 Reserved Area
- 3. Memory
- 4. Special Function Registers (SFRs)
- 5. Reset
- 6. Processor Mode
- 7. Clock Generation Circuit
- 8. Protection
- 9. Interrupt
- 10. Watchdog Timer
- 11. DMAC
- 12. Timer
- 13. Serial I/O
- 14. A/D Converter
- 15. CRC Calculation Circuit
- 16. Programmable I/O Ports
- 16.1 Port Pi Direction Register (PDi Register, i = 1, 6 to 10)
- 16.2 Port Pi Register (Pi Register, i = 1, 6 to 10)
- 16.3 Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers)
- 16.4 Port Control Register
- 16.5 Pin Assignment Control register (PACR)
- 16.6 Digital Debounce function
- 17. Flash Memory Version
- 17.1 Flash Memory Performance
- 17.2 Memory Map
- 17.3 Functions To Prevent Flash Memory from Rewriting
- 17.4 CPU Rewrite Mode
- 17.5 Register Description
- 17.6 Precautions in CPU Rewrite Mode
- 17.6.1 Operation Speed
- 17.6.2 Prohibited Instructions
- 17.6.3 Interrupts
- 17.6.4 How to Access
- 17.6.5 Writing in the User ROM Space
- 17.6.6 DMA Transfer
- 17.6.7 Writing Command and Data
- 17.6.8 Wait Mode
- 17.6.9 Stop Mode
- 17.6.10 Low Power Consumption Mode and On-chip Oscillator-Low Power Consumption Mode
- 17.7 Software Commands
- 17.8 Status Register
- 17.9 Standard Serial I/O Mode
- 17.10 Parallel I/O Mode
- 18. Electrical Characteristics
- 19. Usage Notes
- 19.1 SFR
- 19.2 PLL Frequency Synthesizer
- 19.3 Power Control
- 19.4 Protect
- 19.5 Interrupts
- 19.6 DMAC
- 19.7 Timer
- 19.8 Serial I/O
- 19.9 A/D Converter
- 19.10 Programmable I/O Ports
- 19.11 Electric Characteristic Differences Between Mask ROM
- 19.12 Mask ROM Version
- 19.13 Flash Memory Version
- 19.13.1 Functions to Inhibit Rewriting Flash Memory
- 19.13.2 Stop mode
- 19.13.3 Wait mode
- 19.13.4 Low power dissipation mode, on-chip oscillator low power dissipation mode
- 19.13.5 Writing command and data
- 19.13.6 Program Command
- 19.13.7 Operation speed
- 19.13.8 Instructions prohibited in EW0 Mode
- 19.13.9 Interrupts
- 19.13.10 How to access
- 19.13.11 Writing in the user ROM area
- 19.13.12 DMA transfer
- 19.13.13 Regarding Programming/Erasure Times and Execution Time
- 19.13.14 Definition of Programming/Erasure Times
- 19.13.15 Flash Memory Version Electrical Characteristics 10,000 E/W cycle product
- 19.13.16 Boot Mode
- 19.14 Noise
- 19.15 Instruction for a Device Use
- Appendix 1. Package Dimensions
- Appendix 2. Functional Difference
- Register Index
- REVISION HISTORY

12. Timer
page 126
923fo7002,51.beF00.2.veR
0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
Figure 12.3.9. Triangular Wave Modulation Operation
The three-phase motor control timer function is enabled by setting the INV02 bit in the VC0 register to “1”.
When this function is on, timer B2 is used to control the carrier wave, and timers A4, A1 and A2 are used to
__ ___ ___
control three-phase PWM outputs (U, U, V, V, W and W). The dead time is controlled by a dedicated dead-
time timer. Figure 12.3.9 shows the example of triangular modulation waveform, and Figure 12.3.10 shows
the example of sawtooth modulation waveform.
Start trigger signal
for timer A4
(1)
Timer B2
U phase
Triangular wave
Signal wave
U phase
output signal
(1)
m
nn
p
p
m
U phase
U phase
U phase
INV14 = 0
Triangular waveform as a Carrier Wave
Timer A4
one-shot pulse
(1)
INV14 = 1
Dead time
Dead time
Rewrite registers IDB0 and IDB1
NOTE:
1. Internal signals. See Figure 12.3.1.
Examples of PWM output change are:
(1)When INV11 = 1 (three-phase mode 1)
· INV01 = 0 and ICTB2 = 2
16
(the timer B2 interrupt is generated
every two times the timer B2 underflows),
or INV01 = 1, INV00 = 1, and ICTB2=1
16
(the timer B2 interrupt is
generated at the falling edge of the timer A1 reload control signal.)
· Default value of the timer: TA41 = m, TA4 = m.
Registers TA4 and TA41 are changed whenever the timer B2
interrupt is generated.
First time, TA41 = n, TA4 = n. Second time, TA41 = p, TA4 = p.
· Default values of registers IDB0 and IDB1:
DU0 = 1, DUB0 = 0, DU1 = 0, DUB1 = 1.
They are changed to DU0 = 1, DUB0 = 0, DU1= 1 and DUB1 = 0
when the third timer B2 interrupt is generated.
(2)When INV11 = 0 (three-phase mode 0)
· INV01 = 0, ICTB2 = 1
16
(the timer B2 interrupt is generated
whenever timer B2 underflows)
· Default value of the timer: TA4 = m. The TA4 register is changed
whenever the timer B2 interrupt is generated.
First time: TA4 = m. Second tim:, TA4 = n.
Third time: TA4 = n. Fourth time: TA4 = p.
Fifth time: TA4 = p.
· Default values of registers IDB0 and IDB1:
DU0 = 1, DUB0 = 0, DU1 = 0, DUB1 = 1.
They are changed to DU0 = 1, DUB0 = 0, DU1 = 1, and DUB1 = 0
when the sixth timer B2 interrupt is generated.
TB2S bit in the
TABSR register
INV13
(INV11=1(three-phase
mode 1))
The above applies under the following conditions:
INVC0 = 00XX11XX
2
(X varies depending on each system) and INVC1 = 010XXXX0
2
.
U phase
output signal
(1)
(“L” active)
(“H” active)
The value written to registers TA4 and TA41 becomes effective at the rising edge of the timer A1 reload control signal.
Transfer the values
to the three-phase
output shift register