Datasheet
Table Of Contents
- Notes regarding these materials
- General Precautions in the Handling of MPU/MCU Products
- How to Use This Manual
- Table of Contents
- Quick Reference by Address B-
- 1. Overview
- 2. Central Processing Unit (CPU)
- 2.1 Data Registers (R0, R1, R2 and R3)
- 2.2 Address Registers (A0 and A1)
- 2.3 Frame Base Register (FB)
- 2.4 Interrupt Table Register (INTB)
- 2.5 Program Counter (PC)
- 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
- 2.7 Static Base Register (SB)
- 2.8 Flag Register (FLG)
- 2.8.1 Carry Flag (C Flag)
- 2.8.2 Debug Flag (D Flag)
- 2.8.3 Zero Flag (Z Flag)
- 2.8.4 Sign Flag (S Flag)
- 2.8.5 Register Bank Select Flag (B Flag)
- 2.8.6 Overflow Flag (O Flag)
- 2.8.7 Interrupt Enable Flag (I Flag)
- 2.8.8 Stack Pointer Select Flag (U Flag)
- 2.8.9 Processor Interrupt Priority Level (IPL)
- 2.8.10 Reserved Area
- 3. Memory
- 4. Special Function Registers (SFRs)
- 5. Reset
- 6. Processor Mode
- 7. Clock Generation Circuit
- 8. Protection
- 9. Interrupt
- 10. Watchdog Timer
- 11. DMAC
- 12. Timer
- 13. Serial I/O
- 14. A/D Converter
- 15. CRC Calculation Circuit
- 16. Programmable I/O Ports
- 16.1 Port Pi Direction Register (PDi Register, i = 1, 6 to 10)
- 16.2 Port Pi Register (Pi Register, i = 1, 6 to 10)
- 16.3 Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers)
- 16.4 Port Control Register
- 16.5 Pin Assignment Control register (PACR)
- 16.6 Digital Debounce function
- 17. Flash Memory Version
- 17.1 Flash Memory Performance
- 17.2 Memory Map
- 17.3 Functions To Prevent Flash Memory from Rewriting
- 17.4 CPU Rewrite Mode
- 17.5 Register Description
- 17.6 Precautions in CPU Rewrite Mode
- 17.6.1 Operation Speed
- 17.6.2 Prohibited Instructions
- 17.6.3 Interrupts
- 17.6.4 How to Access
- 17.6.5 Writing in the User ROM Space
- 17.6.6 DMA Transfer
- 17.6.7 Writing Command and Data
- 17.6.8 Wait Mode
- 17.6.9 Stop Mode
- 17.6.10 Low Power Consumption Mode and On-chip Oscillator-Low Power Consumption Mode
- 17.7 Software Commands
- 17.8 Status Register
- 17.9 Standard Serial I/O Mode
- 17.10 Parallel I/O Mode
- 18. Electrical Characteristics
- 19. Usage Notes
- 19.1 SFR
- 19.2 PLL Frequency Synthesizer
- 19.3 Power Control
- 19.4 Protect
- 19.5 Interrupts
- 19.6 DMAC
- 19.7 Timer
- 19.8 Serial I/O
- 19.9 A/D Converter
- 19.10 Programmable I/O Ports
- 19.11 Electric Characteristic Differences Between Mask ROM
- 19.12 Mask ROM Version
- 19.13 Flash Memory Version
- 19.13.1 Functions to Inhibit Rewriting Flash Memory
- 19.13.2 Stop mode
- 19.13.3 Wait mode
- 19.13.4 Low power dissipation mode, on-chip oscillator low power dissipation mode
- 19.13.5 Writing command and data
- 19.13.6 Program Command
- 19.13.7 Operation speed
- 19.13.8 Instructions prohibited in EW0 Mode
- 19.13.9 Interrupts
- 19.13.10 How to access
- 19.13.11 Writing in the user ROM area
- 19.13.12 DMA transfer
- 19.13.13 Regarding Programming/Erasure Times and Execution Time
- 19.13.14 Definition of Programming/Erasure Times
- 19.13.15 Flash Memory Version Electrical Characteristics 10,000 E/W cycle product
- 19.13.16 Boot Mode
- 19.14 Noise
- 19.15 Instruction for a Device Use
- Appendix 1. Package Dimensions
- Appendix 2. Functional Difference
- Register Index
- REVISION HISTORY

12. Timer
page 120
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0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
Figure 12.3.3. INVC1 Register
Three-phase PWM control register 1
(1)
Symbol Address After reset
INVC1 0349
16 0016
b7 b6 b5 b4 b3 b2 b1 b0
Timer A1, A2, A4 start
trigger signal select bit
INV10
Bit symbol Bit name Description
RW
INV11
Timer A1-1, A2-1, A4-1
control bit
INV12
Dead time timer count
source select bit
INV14 Output polarity control bit
(b7)
Reserved bit
INV16
Dead time timer trigger
select bit
INV15 Dead time invalid bit
INV13
Carrier wave detect flag
0: Timer B2 underflow
1: Timer B2 underflow and write to the
TB2 register
0: Three-phase mode 0
1: Three-phase mode 1
0 : f
1 or f2
1 : f1 divided by 2 or f2 divided by 2
0: Timer A1 reload control signal is “0”
1: Timer A1 reload control signal is “1”
0 : Output waveform “L” active
1 : Output waveform “H” active
0: Dead time timer enabled
1: Dead time timer disabled
0: Falling edge of timer A4, A1 or A2
one-shot pulse
1: Rising edge of three-phase output shift
register (U, V or W phase) output
This bit should be set to “0”
(6)
(5)
RW
RW
RW
RW
RW
RW
RW
RO
(3)
Item
Mode
TA11, TA21, TA41 registers
INV00 bit, INV01 bit
INV13 bit
INV11=0
Three-phase mode 1
Three-phase mode 0
Not used
Has no effect. ICTB2 counted every time
timer B2 underflows regardless of
whether the INV00 to INV01 bits are set.
Has no effect
INV11=1
Used
Effect
Effective when INV11 bit is set to “1”
and INV06 bit is set to “0”
(4)
0
(2)
4. If the INV06 bit is set to “1” (sawtooth wave modulation mode), set this bit to “0” (three-phase mode 0). Also, if the
INV11 bit is “0”, set the PWCON bit to “0” (timer B2 reloaded by a timer B2 underflow).
5. The INV13 bit is effective only when the INV06 bit is set to “0” (triangular wave modulation mode) and the INV11 bit is
set to “1” (three-phase mode 1).
6. If all of the following conditions hold true, set the INV16 bit to “1” (dead time timer triggered by the rising edge of
three-phase output shift register output) • The INV15 bit is set to “0” (dead time timer enabled) • When the INV03 bit is
set to “1” (three-phase motor control timer output enabled), the Dij bit and DiBj bit (i:U, V, or W, j: 0 to 1) have always
different values (the positive-phase and negative-phase always output different levels during the period other than
dead time).
Conversely, if either one of the above conditions holds false, set the INV16 bit to “0” (dead time timer triggered by the
falling edge of one-shot pulse).
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to “1” (write enable). Note also that this register
can only be rewritten when timers A1, A2, A4 and B2 are idle.
2. A start trigger is generated by writing to the TB2 register only while timer B2 stops.
3. The effects of the INV11 bit are described in the table below.