Datasheet

12. Timer
page 119
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0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
Figure 12.3.2. INVC0 Register
Three-phase PWM control register 0 (1)
Symbol Address After reset
INVC0 0348
16 0016
b7 b6 b5 b4 b3 b2 b1 b0
Effective interrupt output
polarity select bit
INV00
Bit symbol Bit name Description
RW
INV01
Effective interrupt output
specification bit
INV02
Mode select bit
INV04
Positive and negative
phases concurrent output
disable bit
INV07 Software trigger select bit
INV06
Modulation mode select
bit
INV05
Positive and negative
phases concurrent output
detect flag
INV03
Output control bit
0: The ICTB2 counter is incremented by
one on the rising edge of the timer A1
reload control signal
1: The ICTB2 counter is incremented by
one on the falling edge of the timer A1
reload control signal
0:
ICTB2 counter incremented by 1 at a
timer B2 underflow
1: Selected by INV00 bit
0: Three-phase motor control timer
function unused
1: Three-phase motor control timer
function
0: Three-phase motor control timer output
disabled
1: Three-phase motor control timer output
enabled
0: Simultaneous active output enabled
1: Simultaneous active output disabled
0: Not detected yet
1: Already detected
0: Triangular wave modulation mode
1: Sawtooth wave modulation mode
Setting this bit to “1” generates a transfer
trigger. If the INV06 bit is “1”, a trigger for
the dead time timer is also generated.
The value of this bit when read is “0”.
(9)
(3)
(7)
(2, 3)
n
(4)
RW
RW
RW
RW
RW
RW
RW
RW
(5)
(8)
Item
Mode
Timing at which transferred from IDB0 to
IDB1 registers to three-phase output shift
register
Timing at which dead time timer trigger is
generated when INV16 bit is “0”
INV13 bit
INV06=0
Triangular wave modulation mode
Transferred only once synchronously
with the transfer trigger after writing to
the IDB0 to IDB1 registers
Synchronous with the falling edge of
timer A1, A2, or A4 one-shot pulse
Effective when INV11 is “1” and INV06
is “0”
INV06=1
Sawtooth wave modulation mode
Transferred every transfer trigger
Synchronous with the transfer
trigger and the falling edge of timer
A1, A2, or A4 one-shot pulse
Transfer trigger: Timer B2 underflow, write to the INV07 bit or write to the TB2 register when INV10 is “1”
(6)
Has no effect
(10)
(5)
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to “1” (write enable). Note also that INV00 to INV02,
INV04 and INV06 bits can only be rewritten when timers A1, A2, A4 and B2 are idle.
2. If this bit needs to be set to “1”, set any value in the ICTB2 register before writing to it.
3. Effective when the INV11 bit is set to “1” (three-phase mode 1). If INV11 is set to “0” (three-phase mode 0), the ICTB2
counter is incremented by “1” each time the timer B2 underflows, regardless of whether the INV00 and INV01 bits are set.
When setting the INV01 bit to “1”, set the timer A1 count start flag before the first timer B2 underflow.When the INV00 bit is
set to “1”, the first interrupt is generated when the timer B2 underflows n-1 times, if n is the value set in the ICTB2 counter.
Subsequent interrupts are generated every n times the timer B2 underflow.
4. Setting the INV02 bit to “1” activates the dead time timer, U/V/W-phase output control circuits and ICTB2 counter.
5. When the INV02 bit is set to “1”(theee-phase control timer functions) and the INV03 is set to "0"(three-phase motor control
timer output disabled), U, U, V, V, W and W pins, including pins shared with other output functions, enter a high-impedance
state.
6. The INV03 bit is set to “0” in the following cases:
• When reset
• When positive and negative go active (INV05="1") simultaneously while INV04 bit is set to “1”
• When set to “0” in a program
• When input on the SD pin changes state from “H” to “L” (The INV03 bit cannot be set to “1” when SD input is “L”.) When
both the INV04 and the INV05 bits are set to “1”, the INV03 bit is set to “0”.
7. Can only be set by writing “0” in a program, and cannot be set to “1”.
8. The effects of the INV06 bit are described in the table below.
9. If the INV06 bit is “1”, set the INV11 bit to “0” (three-phase mode 0) and set the PWCON bit to “0” (timer B2 reloaded by a
timer B2 underflow).
10. Individual pins can be disabled using PFCR register.