Datasheet
Table Of Contents
- Notes regarding these materials
- General Precautions in the Handling of MPU/MCU Products
- How to Use This Manual
- Table of Contents
- Quick Reference by Address B-
- 1. Overview
- 2. Central Processing Unit (CPU)
- 2.1 Data Registers (R0, R1, R2 and R3)
- 2.2 Address Registers (A0 and A1)
- 2.3 Frame Base Register (FB)
- 2.4 Interrupt Table Register (INTB)
- 2.5 Program Counter (PC)
- 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
- 2.7 Static Base Register (SB)
- 2.8 Flag Register (FLG)
- 2.8.1 Carry Flag (C Flag)
- 2.8.2 Debug Flag (D Flag)
- 2.8.3 Zero Flag (Z Flag)
- 2.8.4 Sign Flag (S Flag)
- 2.8.5 Register Bank Select Flag (B Flag)
- 2.8.6 Overflow Flag (O Flag)
- 2.8.7 Interrupt Enable Flag (I Flag)
- 2.8.8 Stack Pointer Select Flag (U Flag)
- 2.8.9 Processor Interrupt Priority Level (IPL)
- 2.8.10 Reserved Area
- 3. Memory
- 4. Special Function Registers (SFRs)
- 5. Reset
- 6. Processor Mode
- 7. Clock Generation Circuit
- 8. Protection
- 9. Interrupt
- 10. Watchdog Timer
- 11. DMAC
- 12. Timer
- 13. Serial I/O
- 14. A/D Converter
- 15. CRC Calculation Circuit
- 16. Programmable I/O Ports
- 16.1 Port Pi Direction Register (PDi Register, i = 1, 6 to 10)
- 16.2 Port Pi Register (Pi Register, i = 1, 6 to 10)
- 16.3 Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers)
- 16.4 Port Control Register
- 16.5 Pin Assignment Control register (PACR)
- 16.6 Digital Debounce function
- 17. Flash Memory Version
- 17.1 Flash Memory Performance
- 17.2 Memory Map
- 17.3 Functions To Prevent Flash Memory from Rewriting
- 17.4 CPU Rewrite Mode
- 17.5 Register Description
- 17.6 Precautions in CPU Rewrite Mode
- 17.6.1 Operation Speed
- 17.6.2 Prohibited Instructions
- 17.6.3 Interrupts
- 17.6.4 How to Access
- 17.6.5 Writing in the User ROM Space
- 17.6.6 DMA Transfer
- 17.6.7 Writing Command and Data
- 17.6.8 Wait Mode
- 17.6.9 Stop Mode
- 17.6.10 Low Power Consumption Mode and On-chip Oscillator-Low Power Consumption Mode
- 17.7 Software Commands
- 17.8 Status Register
- 17.9 Standard Serial I/O Mode
- 17.10 Parallel I/O Mode
- 18. Electrical Characteristics
- 19. Usage Notes
- 19.1 SFR
- 19.2 PLL Frequency Synthesizer
- 19.3 Power Control
- 19.4 Protect
- 19.5 Interrupts
- 19.6 DMAC
- 19.7 Timer
- 19.8 Serial I/O
- 19.9 A/D Converter
- 19.10 Programmable I/O Ports
- 19.11 Electric Characteristic Differences Between Mask ROM
- 19.12 Mask ROM Version
- 19.13 Flash Memory Version
- 19.13.1 Functions to Inhibit Rewriting Flash Memory
- 19.13.2 Stop mode
- 19.13.3 Wait mode
- 19.13.4 Low power dissipation mode, on-chip oscillator low power dissipation mode
- 19.13.5 Writing command and data
- 19.13.6 Program Command
- 19.13.7 Operation speed
- 19.13.8 Instructions prohibited in EW0 Mode
- 19.13.9 Interrupts
- 19.13.10 How to access
- 19.13.11 Writing in the user ROM area
- 19.13.12 DMA transfer
- 19.13.13 Regarding Programming/Erasure Times and Execution Time
- 19.13.14 Definition of Programming/Erasure Times
- 19.13.15 Flash Memory Version Electrical Characteristics 10,000 E/W cycle product
- 19.13.16 Boot Mode
- 19.14 Noise
- 19.15 Instruction for a Device Use
- Appendix 1. Package Dimensions
- Appendix 2. Functional Difference
- Register Index
- REVISION HISTORY
12. Timer
page 118
923fo7002,51.beF00.2.veR
0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
D
R
Q
0
INV12
1
T
ri
g
ge
r
T
ri
g
ge
r
Timer B2
(T
i
mer mo
d
e
)
S
ignal to b
e
written to
timer B2
1
Timer B2
interrupt
reque
st bit
DU1
b
it
D
T
Q
Q
Q
U
Three-phase output
shift register
(U phase)
Dead time timer
n = 1
to 255
T
ri
gg
er
T
ri
gge
r
Reload register
n = 1
to 255
T
ri
gg
er
Trigg
er
U
phase output signal
U
V
V
V
W
W
W
phase output
control circuit
D
Q
T
D
Q
T
W
D
Q
T
D
Q
T
V
D
Q
T
D
Q
T
U
W
V
U
Reload
Timer A 1 counter
(One-shot
timer mode)
T
ri
g
ge
r
T
Q
Reload
Timer A2
counter
(One-shot
time
r mode)
T
ri
g
ge
r
T
Q
Reload
Timer A4 counter
(One-shot
time
r mode)
T
ri
g
ger
T
Q
T
r
a
nsfer
trig
g
er
(
N
ot
e
1
)
T
imer
B2
u
nderflow
D
U0
bit
D
UB0
bit
TA4 register
TA41
register
TA1
register
TA11
register
TA2
register
TA21
register
Timer Ai(i = 1, 2, 4) start trigger signal
Timer A4 reload control signal
Timer A4
one-shot pulse
DUB1
bit
Dead time timer
n
= 1 to 255
Dead time timer
n = 1 to 255
Interrupt occurrence set circuit
ICTB2 register
n = 1 to 15
0
INV13
ICTB2 counter
n = 1 to 15
SD
RESET
INV03
INV14
INV05
INV04
INV00
INV01
INV11
INV11
INV11
INV11
INV06
INV06
INV06
INV07
INV10
1/2
f1 or f2
phase output
control circuit
p
hase output
control circuit
ph
ase output signal
ph
ase output signal
phase output
signal
phase
output signal
ph
ase output signal
Reverse
control
Reverse
control
R
everse
control
Reverse
control
Reverse
control
D
T
D
T
Q
D
T
Reverse
control
IDW
IDV
IDU
D
Q
T
D
Q
T
D
Q
T
b2
b0
b1
Bits 2 through 0 of Position-data-
retain function control register
(address 034E
16
)
PD8_0
PD8_1
PD7_2
PD7_3
PD7_4
PD7_5
S
Q
R
RESET
SD
IVPRC1
Data Bus
NOTE:
1. If the INV06 bit is set to "0" (triangular wave modulation mode), a transfer trigger is generated at only the first occurrence of a timer B2 underflow after writing to the IDB0 and IDB1 registers.
Set to "0" when the TA2S bit is set to "0"
Set to "0" when TA1S bit = "0"
Set to "0" when TA4S bit = "0"
Diagram for switching to P8
0
, P81 and P7
2
- P7
5
is not shown.
Figure 12.3.1. Three-phase Motor Control Timer Functions Block Diagram