Datasheet

12. Timer
page 116
923fo7002,51.beF00.2.veR
0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
Timer Bi mode register (i= 0 to 1)
Symbol Address After reset
TB0MR to TB1MR 039B
16 to 039C16 00XX00002
Bit name Function
Bit symbol
RW
b7 b6 b5 b4 b3 b2 b1 b0
Operation Mode Select Bit
0 0 : Timer mode or A/D trigger mode
b1 b0
TMOD1
TMOD0
MR0
Invalid in A/D trigger mode
Either "0" or "1" is enabled
MR2
MR1
MR3
0 0 : f
1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
TCK1
TCK0
Count Source Select Bit
(1)
00
TB0MR register
Set to “0” in A/D trigger mode
b7 b6
RW
RW
RW
RW
RW
RW
RW
RO
TB1MR register
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate
When write in A/D trigger mode, set to “0”. When read in A/D
trigger mode, its content is indeterminate.
NOTE:
1. When this bit is used in dela
y
ed tri
gg
er mode 0, set the same count source to the timer B0 and timer B1.
Figure 12.2.4.1 TBiMR Register in A/D Trigger Mode
PWCOM
Symbol Address After reset
TB2SC 039E
16 X00000002
Timer B2 Reload Timing
Switch Bit
0 : Timer B2 underflow
1 : Timer A output at odd-numbered
Timer B2 special mode register
(1)
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
IVPCR1
Three-Phase Output Port
SD Control Bit 1
0 : Three-phase output forcible cutoff
by SD pin input (high impedance)
disabled
1 : Three-phase output forcible cutoff
by SD pin input (high impedance)
enabled
RW
RW
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7)
TB2SEL
Trigger Select Bit
0 : TB2 interrupt
1 : Underflow of TB2 interrupt
generation frequency setting counter [ICTB2]
RW
RW
TB0EN
Timer B0 Operation Mode
Select Bit
0 : Other than A/D trigger mode
1 : A/D trigger mode
(5)
RW
TB1EN
Timer B1 Operation Mode
Select Bit
0 : Other than A/D trigger mode
1 : A/D trigger mode
(5)
RW
(2)
(3, 4, 7)
(6)
(b6-b5)
Reserved bits Must set to "0"
0
0
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enabled).
2. If the INV11 bit is "0" (three-phase mode 0) or the INV06 bit is "1" (triangular wave modulation mode), set this bit to
"0" (timer B2 underflow).
3. When setting the IVPCR1 bit to "1" (three-phase output forcible cutoff by SD pin input enabled), Set the PD8_5 bit to
"0" (= input mode).
4. Related pins are U(P8
0 ), U(P8 1 ), V(P7 2 ), V(P7 3 ), W(P7 4 ), W(P7 5 ). When a high-level ("H") signal is applied to the SD
pin and set the IVPCR1 bit to 0 after forcible cutoff, pins U, U, V, V, W, and W are exit from the high-impedance state.
If a low-level (“L”) signal is applied to the SD pin, three-phase motor control timer output will be disabled (INV03=0).
At this time, when the IVPCR1 bit is 0, pins U, U, V, V, W, and W become programmable I/O ports. When the IVPCR1
bit is set to 1, pins U, U, V, V, W, and W are placed in a high-impedance state regardless of which function of those
pins is used.
5. When this bit is used in delayed trigger mode 0, set the TB0EN and TB1EN bits to "1"(A/D trigger mode).
6. When setting the TB2SEL bit to "1" (underflow of TB2 interrupt generation frequency setting counter[ICTB2]), Set the
INV02 bit to "1" (three-phase motor control timer function).
7. Refer to 16.6 Di
g
ital Debounce function for SD in
p
ut.
Figure 12.2.4.2 TB2SC Register