Datasheet

12. Timer
page 114
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Figure 12.2.3.3 Operation timing when measuring a pulse width
Measurement pulse
“H”
Count source
Timing at which counter
reaches “0000
16 ”
“1”
“1
”
Transfer
(measured value)
Transfer
(measured value)
“L”
“0”
“0
”
“1”
“0
”
(1)(1)
(1)
Transfer
(measured
value)
(1)
(2)
Transfer
(indeterminate
value)
Reload register counter
transfer timing
TBiS bit
IR bit in the TBiIC
register
MR3 bit in the TBiMR
register
The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.
Set to “0” upon accepting an interrupt request or by
writing in program
i = 0 to 2
NOTES:
1. Counter is initialized at completion of measurement.
2. Timer has overflowed.
3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are “10
2 ” (measure the
interval from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of
the measurement pulse).
Figure 12.2.3.2 Operation timing when measuring a pulse period
Count source
Measurement pulse
TBiS bit
IR bit in the TBiIC
register
Timing at which counter
reaches “0000
16 ”
“H”
“1”
Transfer
(indeterminate value)
“L”
“0”
“0”
MR3 bit in theTBiMR
register
“1”
“0
”
(1)(1)
(2)
Transfer
(measured value)
“1”
Reload register counter
transfer timing
The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.
Set to “0” upon accepting an interrupt request or by writing in
program
i = 0 to 2
NOTES:
1. Counter is initialized at completion of measurement.
2. Timer has overflowed.
3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are “00
2 ” (measure the interval
from falling edge to falling edge of the measurement pulse).