Datasheet

12. Timer
page 112
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Item Specification
Count source • External signals input to TBiIN pin (i=0 to 2) (effective edge can be selected
in program)
• Timer Bj overflow or underflow (j=i-1, except j=2 if i=0)
Count operation • Down-count
• When the timer underflows, it reloads the reload register contents and
continues counting
Divide ratio 1/(n+1) n: set value of TBi register 000016 to FFFF16
Count start condition Set TBiS bit
(1)
to “1” (= start counting)
Count stop condition Set TBiS bit to “0” (= stop counting)
Interrupt request generation timing Timer underflow
TBiIN pin function Count source input
Read from timer Count value can be read by reading TBi register
Write to timer • When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
NOTE:
1. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.
12.2.2 Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers (see Table 12.2.2.1) . Figure 12.2.2.1 shows TBiMR register in event counter mode.
Table 12.2.2.1 Specifications in Event Counter Mode
Figure 12.2.2.1 TBiMR Register in Event Counter Mode
Timer Bi mode register (i=0 to 2)
Symbol Address After reset
TB0MR to TB2MR 039B
16 to 039D 16 00XX0000 2
Bit name FunctionBit symbol
RW
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode select bit
0 1 : Event counter mode
b1 b0
TMOD1
TMOD0
MR0 Count polarity select
bit
(1)
MR2
MR1
MR3
TCK1
TCK0
01
0 0 : Counts external signal's
falling edges
0 1 : Counts external signal's
rising edges
1 0 : Counts external signal's
falling and rising edges
1 1 : Must not be set
b3 b2
Has no effect in event counter mode.
Can be set to “0” or “1”.
Event clock select
0 : Input from TBi
IN pin
(2)
1 : TBj overflow or underflow
(j = i – 1, except j = 2 if i = 0)
RW
RW
RW
RW
RW
RW
RW
RO
TB0MR register
Must be set to “0” in timer mode
TB1MR, TB2MR registers
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate.
When write in event counter mode, set to “0”. When read in event
counter mode, its content is indeterminate.
NOTES:
1. Effective when the TCK1 bit is set to “0” (input from TBiIN pin). If the TCK1 bit is set to “1” (TBj overflow or underflow), these bits
can be set to “0” or “1”.
2. The port direction bit for the TBiIN pin must be set to “0” (= input mode).