Datasheet

Table Of Contents
12. Timer
page 108
923fo7002,51.beF00.2.veR
0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
Figure 12.2.1. Timer B Block Diagram
12.2 Timer B
Note
The TB2IN pin for Timer B2 is not available in 42-pin package.
[Precautions when using Timer B2]
Event Counter Mode The external input signals cannot be counted. Set the TCK1 bit in the
TB2MR register to 1 when using the Event Count Mode.
Pulse Period/Pulse Width Measurement Mode
This mode connot be used.
Figure 12.2.1 shows a block diagram of the timer B. Figures 12.2.2 and 12.2.3 show registers related to the
timer B.
Timer B supports the following four modes. Use the TMOD1 and TMOD0 bits in the TBiMR register (i = 0 to
2) to select the desired mode.
Timer mode: The timer counts an internal count source.
Event counter mode: The timer counts pulses from an external device or overflows or underflows of
other timers.
Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or
pulse width.
A/D trigger mode: The timer starts counting by one trigger until the count value becomes 000016.
This mode is used together with simultaneous sample sweep mode or delayed trigger mode 0 of A/D
converter to start A/D conversion.
Clock source selection
Event counter
Reload register
Low-order 8 bits
High-order 8 bits
Data bus low-order bits
Data bus high-order bits
f
8
TABSR register
Polarity switching,
edge pulse
Counter reset circuit
Counter
Clock selection
Timer mode
Pulse period/, pulse width measuring mode
A/D trigger mode
f
1
or f
2
f
C32
f
32
TBj overflow
(1)
(j = i 1, except j = 2 if i = 0)
Can be selected in
onlyevent counter mode
TBi
IN
(i = 0 to 2)
NOTE:
1. Overflow or underflow.
TBi Address TBj
Timer B0 0391
16
-
0390
16
Timer B2
Timer B1 0393
16 -
0392
16
Timer B0
Timer B2 0395
16 -
0394
16
Timer B1