Datasheet

12. Timer
page 106
923fo7002,51.beF00.2.veR
0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
Figure 12.1.4.1. TAiMR Register in Pulse Width Modulation Mode
Bit name
Timer Ai mode register (i= 0 to 4)
Symbol Address After reset
TA0MR to TA4MR 0396
16 to 039A16 0016
FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode
select bit
1 1 : PWM mode
b1 b0
TMOD1
TMOD0
MR
0
MR2
MR
1
MR
3
0 0 : f
1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
b7 b6
TCK1
TCK0
Count source select bit
R
W
111
16/8-bit PWM mode
select bit
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
Trigger select bit
External trigger select
bit
(1)
0: Falling edge of input signal to TAiIN pin
(2)
1: Rising edge of input signal to TAiIN pin
(2)
RW
RW
RW
RW
RW
RW
RW
RW
0 : Write “1” to TAiS bit in the TASF register
1 : Selected by TAiTGH to TAiTGL bits
0: Pulse is not output (TAiOUT pin functions as I/O port)
1: Pulse is output (TAiOUT pin functions as a pulse output
pin)
Pulse output funcion
select bit
NOTES:
1. Effective when the TAiTGH and TAiTGL bits in the ONSF or TRGSR register are ‘00
2’ (TAiIN pin input).
2. The port direction bit for the TAi
IN pin must be set to “0” (= input mode).