Datasheet

12. Timer
page 102
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0020-2020B90JER
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m m+1 1 2 3 4 5
TA3
OUT
(A phase)
Count source
TA3
IN
(B phase)
Timer A3
INT2
(Z phase)
(1)
Input equal to or greater than one clock cycle
of count source
NOTE:
1. This timing diagram is for the case where the POL bit in the INT2IC register is set to “1” (= rising edge).
12.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing
This function initializes the timer count value to “0” by Z-phase (counter initialization) input during two-
phase pulse signal processing.
This function can only be used in timer A3 event counter mode during two-phase pulse signal process-
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ing, free-running type, x4 processing, with Z-phase entered from the INT2 pin.
Counter initialization by Z-phase input is enabled by writing “000016” to the TA3 register and setting
the TAZIE bit in ONSF register to “1” (= Z-phase input enabled).
Counter initialization is accomplished by detecting Z-phase input edge. The active edge can be cho-
sen to be the rising or falling edge by using the POL bit in the INT2IC register. The Z-phase pulse width
_______
applied to the INT2 pin must be equal to or greater than one clock cycle of the timer A3 count source.
The counter is initialized at the next count timing after recognizing Z-phase input. Figure 12.1.2.1.1
shows the relationship between the two-phase pulse (A phase and B phase) and the Z phase.
If timer A3 overflow or underflow coincides with the counter initialization by Z-phase input, a timer A3
interrupt request is generated twice in succession. Do not use the timer A3 interrupt when using this
function.
Figure 12.1.2.1.1. Two-phase Pulse (A phase and B phase) and the Z Phase