Datasheet

12. Timer
page 99
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0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
Figure 12.1.2.1. TAiMR Register in Event Counter Mode (when not using two-phase pulse signal
processing)
Symbol Address After reset
TA0MR to TA4MR 0396
16 to 039A 16 00 16
WR
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode select bit
0 1 : Event counter mode
(1)
b1 b0
TMOD0
MR0
Pulse output function
select bit
0 : Pulse is not output
(TA
iOUT pin functions as I/O port)
1 : Pulse is output
(TAi OUT pin functions as pulse output pin)
Count polarity
select bit (2)
MR2
MR1
MR3
Must be set to “0” in event counter mode
TCK0
Count operation type
select bit
010
0 : Counts external signal's falling edge
1 : Counts external signal's rising edge
Up/down switching
cause select bit
0 : UDF register
1 : Input signal to TA
iOUT pin (3)
0 : Reload type
1 : Free-run type
Bit symbol Bit name Function
RW
TCK1
Can be “0” or “1” when not using two-phase pulse signal
processing
TMOD1
Timer Ai mode register (i=0 to 4)
(When not using two-phase pulse signal processing)
RW
RW
RW
RW
RW
RW
RW
RW
NOTES:
1. During event counter mode, the count source can be selected using the ONSF and TRGSR registers.
2. Effective when the TAiTGH and TAiTGL bits in the ONSF or TRGSR register are ‘00
2 ’ (TAi IN pin input).
3. Count down when input on TAi
OUT pin is low or count up when input on that pin is high. The port
direction bit for TAi
OUT pin must be set to “0” (= input mode).