Datasheet

12. Timer
page 96
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0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
Figure 12.1.4. ONSF Register, TRGSR Register, and CPSRF Register
Symbol Address After reset
CPSRF 0381
16 0XXXXXXX 2
Clock prescaler reset flag
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Clock prescaler reset flag
Setting this bit to “1” initializes the
prescaler for the timekeeping clock.
(When read, its content is “0”.)
CPSR
Nothing is assigned.
When write, set to “0”. When read, their contents are
indeterminate.
TA1TGL
Symbol Address After reset
TRGSR 0383
16 00 16
Timer A1 event/trigger
select bit
0 0 :
Input on TA1 IN is selected (1)
0 1 : TB2 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected
Trigger select register
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Input on TA2 IN is selected (1)
0 1 : TB2 overflow is selected
1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected
0 0 :
Input on TA3 IN is selected (1)
0 1 : TB2 overflow is selected
1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected
0 0 :
Input on TA4 IN is selected (1)
0 1 : TB2 overflow is selected
1 0 : TA3 overflow is selected
1 1 : TA0 overflow is selected
Timer A2 event/trigger
select bit
Timer A3 event/trigger
select bit
Timer A4 event/trigger
select bit
TA1TGH
TA2TGL
TA2TGH
TA3TGL
TA3TGH
TA4TGL
TA4TG
H
b1 b0
b3 b2
b5 b4
b7 b6
TA1OS
TA2OS
TA0OS
One-shot start flag
Symbol Address After reset
ONSF 0382
16 00 16
Timer A0 one-shot start flag
Timer A1 one-shot start flag
Timer A2 one-shot start flag
Timer A3 one-shot start flag
Timer A4 one-shot start flag
TA3OS
TA4OS
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
TA0TGL
TA0TGH
0 0 : Input on TA0 IN is selected
0 1 : TB2 overflow is selected
1 0 : TA4 overflow is selected
1 1 : TA1 overflow is selected
Timer A0 event/trigger
select bit
b7 b6
RW
The timer starts counting by setting
this bit to “1” while the TMOD1 to
TMOD0 bits in the TAiMR register
(i = 0 to 4) is set to ‘10
2 ’ (= one-
shot timer mode) and the MR2 bit
in the TAiMR register is set to “0”
(=TAiOS bit enabled). When read,
its content is “0”.
Z-phase input enable bit
TAZIE
0 : Z-phase input disabled
1 : Z-phase input enabled
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
(b6-b0)
(2)
(2)
(2)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
NOTES:
1. Make sure the port direction bits for the TA1
IN to TA4 IN pins are set to “0” (= input mode).
2. Overflow or underflow.
NOTES:
1. Make sure the PD7_1 bit in the PD7 register is set to “0” (= input mode).
2. Overflow or underflow.