Datasheet

11. DMAC
page 89
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11.2. DMA Transfer Cycles
Any combination of even or odd transfer read and write adresses is possible. Table 11.2.1 shows the
number of DMA transfer cycles. Table 11.2.2 shows the Coefficient j, k.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 11.2.1 DMA Transfer Cycles
Table 11.2.2 Coefficient j, k
Transfer unit Access address No. of read cycles No. of write cycles
8-bit transfers Even 1 1
(DMBIT= “1”) Odd 1 1
16-bit transfers Even 1 1
(DMBIT= “0”) Odd 2 2
Internal area
Internal ROM, RAM SFR
No wait With wait
1
1
2
2
2
2
j
k
1 wait
2 wait
3
3
(1)
(1)
NOTE:
1. Depends on the set value of PM20 bit in PM2 register.