Datasheet

11. DMAC
page 88
923fo7002,51.beF00.2.veR
0020-2020B90JER
)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M
Figure 11.1.1 Transfer Cycles for Source Read
CPU clock
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use CPU use
CPU useSource
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use CPU use
CPU use
Source
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
(3) When the source read cycle under condition (1) has one wait state inserted
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use
CPU use
CPU useSource
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
Source + 1
Source + 1
(2) When the transfer unit is 16 bits and the source address of transfer is an odd address
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use
CPU use
CPU useSource
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
Source + 1
Source + 1
(4) When the source read cycle under condition (2) has one wait state inserted
CPU clock
CPU clock
CPU clock
NOTE:
1. The same timing changes occur with the respective conditions at the destination as at the source.