Datasheet

11. DMAC
page 84
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Figure 11.2 DM0SL Register
DMA0 request cause select register
Symbol Address After reset
DM0SL 03B8
16 0016
Function
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
DMA request cause
select bit
DSEL0
RW
DSEL1
DSEL2
DSEL3
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
Software DMA
request bit
A DMA request is generated by
setting this bit to “1” when the DMS
bit is “0” (basic cause) and the
DSEL3 to DSEL0 bits are “0001
2”
(software trigger).
The value of this bit when read is “0” .
DSR
DSEL3 to DSEL0 DMS=0(basic cause of request) DMS=1(extended cause of request)
0 0 0 0
2 Falling edge of INT0 pin –
0 0 0 1
2 Software trigger –
0 0 1 0
2 Timer A0 –
0 0 1 1
2 Timer A1 –
0 1 0 0
2 Timer A2 –
0 1 0 1
2 Timer A3 –
0 1 1 0
2 Timer A4 Two edges of INT0 pin
0 1 1 1
2 Timer B0 –
1 0 0 0
2 Timer B1 –
1 0 0 1
2 Timer B2 –
1 0 1 0
2 UART0 transmit –
1 0 1 1
2 UART0 receive –
1 1 0 0
2 UART2 transmit –
1 1 0 1
2 UART2 receive –
1 1 1 0
2 A/D conversion –
1 1 1 1
2 UART1 transmit –
Bit name
DMA request cause
expansion select bit
DMS
0: Basic cause of request
1: Extended cause of request
RW
RW
RW
RW
RW
RW
(b5-b4)
Refer to note
NOTE:
1. The causes of DMA0 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the
manner described below.