Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 48 (7x7) 16-Bit 20 MHz I/O number 39

Table Of Contents

To our customers,

Old Company Name in Catalogs and Other Documents

On April 1

, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corporation took over all the business of both

companies. Therefore, although the old company name remains in this document, it is a valid

Renesas Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1

, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry

Summary of content (354 pages)

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To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
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Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
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Hardware Manual 16 M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Hardware Manual RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp.
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Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2.
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1.
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How to Use This Manual 1. Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual.
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2. Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word “register,” “bit,” or “pin” to distinguish the three categories.
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3. Register Notation The symbols and terms used in register diagrams are described below. XXX Register b7 b6 b5 b4 b3 *1 b2 b1 b0 Symbol XXX 0 Bit Symbol XXX0 Address XXX Bit Name XXX bits XXX1 After Reset 0016 Function RW 1 0: XXX 0 1: XXX 1 0: Do not set. 1 1: XXX RW RW (b2) Nothing is assigned. If necessary, set to 0. When read, the content is undefined. (b3) Reserved bits Set to 0. RW XXX bits Function varies according to the operating mode.
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4.
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Table of Contents Quick Reference by Address _______________________ B-1 1. Overview ______________________________________ 1 1.1 Applications ................................................................................................................... 1 1.2 Performance Outline ..................................................................................................... 2 1.3 Block Diagram .........................................................................................................
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5. Reset ________________________________________ 26 5.1 Hardware Reset .......................................................................................................... 26 5.1.1 Hardware Reset 1 ................................................................................................ 26 5.1.2 Hardware Reset 2 ................................................................................................ 26 5.2 Software Reset .................................................................
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9.2 Interrupts and Interrupt Vector .................................................................................... 64 9.2.1 Fixed Vector Tables .............................................................................................. 64 9.2.2 Relocatable Vector Tables ................................................................................... 65 9.3 Interrupt Control .......................................................................................................... 66 9.3.
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12.3 Three-phase Motor Control Timer Function ............................................................ 117 12.3.1 Position-data-retain Function ........................................................................... 128 12.3.2 Three-phase/Port Output Switch Function ....................................................... 130 13. Serial I/O ___________________________________ 132 13.1. UARTi (i=0 to 2)...................................................................................................
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17.2 Memory Map ........................................................................................................... 232 17.3 Functions To Prevent Flash Memory from Rewriting............................................... 235 17.3.1 ROM Code Protect Function ............................................................................ 235 17.3.2 ID Code Check Function .................................................................................. 235 17.4 CPU Rewrite Mode ..........................
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18. Electrical Characteristics _______________________ 261 18.1. M16C/26A, M16C/26B (Normal version) ................................................................ 261 18.2. M16C/26T (T version) ............................................................................................ 280 19. Usage Notes ________________________________ 299 19.1 SFR ......................................................................................................................... 299 19.1.
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19.13 Flash Memory Version .......................................................................................... 320 19.13.1 Functions to Inhibit Rewriting Flash Memory ................................................. 320 19.13.2 Stop mode ...................................................................................................... 320 19.13.3 Wait mode ...................................................................................................... 320 19.13.
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Quick Reference by Address Address Register Symbol Page Address 000016 004016 000116 004116 000216 004216 000316 000416 000516 000616 000716 000A16 PM0 PM1 CM0 CM1 35 35 40 41 Address match interrupt enable register Protect register AIER PRCR 79 60 Oscillation stop detection register CM2 42 Watchdog timer start register Watchdog timer control register WDTS WDC 81 81 004416 000F16 004816 004916 004C16 004D16 004E16 004F16 005016 RMAD0 79 005116 001216 005216 001316 005316 0
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Quick Reference by Address Address Register Symbol Page Address 008016 034016 008116 034116 008216 034216 008316 034316 008416 034416 008516 034516 008616 034616 Register Symbol Page Timer A1-1 register TA11 122 Timer A2-1 register TA21 122 Timer A4-1 register TA41 122 Three-phase PWM control register 0 Three-phase PWM control register 1 Three-phase output buffer register 0 Three-phase output buffer register 1 Dead time timer Position-data-retain function contol register INVC
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Quick Reference by Address Register Address Symbol Page Address 038016 Count start flag TABSR 95, 110, 124 03C016 038116 Clock prescaler reset flag One-shot start flag Trigger select register Up-down flag CPSRF ONSF TRGSR UDF r 0) 03C216 Timer A0 register TA0 Timer A1 register TA1 95, 122 Timer A2 register TA2 95, 122 Timer A3 register TA3 95 Timer A4 register TA4 95, 122 Timer B0 register TB0 110 Timer B1 register TB1 110 Timer B2 register TB2 Timer A0 mode register Tim
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 1. Overview The M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) is a single-chip control MCU, fabricated using high-performance silicon gate CMOS technology, embedding the M16C/60 Series CPU core. The M16C/ 26A Group (M16C/26A, M16C/26B, M16C/26T) is housed in 42-pin and 48-pin plastic molded packages.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 1. Overview 1.2 Performance Outline Table 1.1 and 1.2 outline performance overview of the M16C/26A Group (M16C/26A, M16C/26B, M16C/ 26T). Table 1.1.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 1. Overview Table 1.2.
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1. Overview M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 1.3 Block Diagram Figure 1.1 and 1.2 show block diagrams of the M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 48pin package and 42-pin package.
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1.
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1. Overview M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 1.4 Product List Tables 1.3 to 1.6 lists product information, Figure 1.3 shows a product numbering system, Table 1.7 lists the product code, and Figure 1.4 shows the marking. Table 1.3 M16C/26A Current as of Feb.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 1. Overview Type No. M 3 0 2 6 0 M 8 A - XXX G P - U3 Product code: See Tables 1.7 to 1.10 Package type: GP: PLQP0048KB-A (48P6Q) (M16C/26A, M16C/26B, M16C/26T) FP: PRSP0042GA-B (42P2R) (M16C/26A, M16C/26B) ROM number: ROM number is omitted in flash memory version Version: A : M16C/26A B : M16C/26B T : M16C/26T T-ver. V : M16C/26T V-ver.
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1. Overview M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Table 1.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 1. Overview (1) Flash memory version, PLQP0048KB-A (48P6Q), M16C/26A, M16C/26B 0260F8A A U3 XXXXX Product Name : indicates M30260F8AGP Chip Version and Product Code: A : Indicates chip version The first edition is shown to be blank and continues with A and B. U3 : Indicates Product code (see Table 1.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 1. Overview (1) Flash memory version, PLQP0048KB-A (48P6Q), M16C/26T T-ver. 0260F8T A U3 XXXXX Product Name : indicates M30260F8TGP Chip Version and Product Code: A : Indicates chip version The first edition is shown to be blank and continues with A and B. U3 : Indicates product code (see Table 1.9 Product Code) Date Code (5 digits) ﬁ indicates manufacturing management code (2) Flash memory version, PLQP0048KB-A (48P6Q), M16C/26T V-ver.
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1. Overview M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 1.5 Pin Assignments P70/TxD2/TA0OUT/SDA2/CTS1/RTS1/CTS0/CLKS1 26 25 P64/CTS1/RTS1/CTS0/CLKS1 P65/CLK1 P66/RxD1 P67/TxD1 28 27 29 31 30 P60/CTS0/RTS0 P61/CLK0 P62/RxD0 P63/TxD0 33 32 34 P15/INT3/ADTRG /IDV P16/INT4/IDW P17/INT5/IDU 35 36 Figures 1.6 and 1.7 show the Pin Assignments (top view).
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1. Overview M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Table 1.11 Pin Characteristics for 48-Pin Package Pin No.
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1.
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1. Overview M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Table 1.12 Pin Characteristics for 42-Pin Package Pin No.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 1. Overview 1.6 Pin Description Table 1.13 Pin Description (48-Pin and 42-Pin Packages) Classification Pin Name Power Supply VCC, VSS Analog Power Supply Reset Input CNVSS Main Clock Input Main Clock Output Sub Clock Input Sub Clock Output Clock Output ______ INT Interrupt Input _______ NMI Interrupt Input I/O Type Description Apply 0V to the Vss pin. Apply following voltage to the Vcc pin. I 2.7 to 5.5 V (M16C/26A, M16C/26B), 3.0 to 5.5 V (M16C/26T T-ver.
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1. Overview M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Table 1.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 2. CPU 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The register bank is comprised of seven registers (R0, R1, R2, R3, A0, A1 and FB) out of 13 registers. There are two sets of register bank.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 2. CPU 2.3 Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 Program Counter (PC) PC is configured with 20 bits, indicating the address of an instruction to be executed. 2.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 3. Memory 3. Memory Figure 3.1 is a memory map of the M16C/26A Group (M16C/26A, M16C/26B, M16C/26T). The M16C/26A Group provides 1-Mbyte address space addresses 0000016 to FFFFF16. The internal ROM is allocated lower address, beginning with address FFFFF16. For example, a 64-Kbyte internal ROM area is allocated in addresses F000016 to FFFFF16. The flash memory version has two sets of 2-Kbyte internal ROM area, block A and block B, for data space.
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4. SFRs M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 4. Special Function Registers (SFRs) Table 4.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 4. SFRs Table 4.
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4. SFRs M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Table 4.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 4. SFRs Table 4.
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4. SFRs M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Table 4.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 4. SFRs Table 4.
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5. Reset M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 5. Reset There are four types of resets: a hardware reset, a software reset, an watchdog timer reset, and an oscillation stop detection reset. 5.1 Hardware Reset There are two types of hardware resets: a hardware reset 1 and a hardware reset 2. 5.1.1 Hardware Reset 1 ____________ ____________ A reset is applied using the RESET pin.
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5. Reset M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Recommended operating voltage VCC 0V RESET VCC RESET Equal to or less than 0.2VCC 0V Equal to or less than 0.2VCC More than td(ROC) + td(P-R) Figure 5.1.1.1. Example Reset Circuit 5.2 Software Reset When the PM03 bit in the PM0 register is set to “1” (microcomputer reset), the microcomputer has its pins, CPU, and SFR initialized. Then the program is executed starting from the address indicated by the reset vector.
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5. Reset M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) VCC ROC td(P-R) More than td(ROC) RESET CPU clock 28 cycles CPU clock FFFFC 16 Address Content of reset vector FFFFE16 Figure 5.1.1.2. Reset Sequence ____________ Table 5.1.1.1.
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5. Reset M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 5.5 Voltage Detection Circuit Note VCC=5 V is assumed. Voltage Detection Circuit is not available in M16C/26T. The voltage detection circuit has circuits to monitor the input voltage at the VCC pin, each checking the input voltage with respect to Vdet3, and Vdet4, respectively. Use the VC26 to VC27 bits in the VCR2 register to select whether or not to enable these circuits. Use the reset level detection circuit for hardware reset 2.
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5. Reset M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Voltage detection register 1 b7 b6 b5 b4 b3 0 0 0 0 b2 b1 b0 0 0 0 Symbol VCR1 Bit symbol Address 001916 After reset (2) 000010002 Bit name F unction RW (b2-b0) Reserved bit Must set to “0” VC13 Voltage down monitor flag (1) 0:VCC < Vdet4 1:VCC ≥ Vdet4 RO (b7-b4) Reserved bit Must set to “0” RW RW NOTES: 1. The VC13 bit is useful when the VC27 bit in the VCR2 register is set to "1" (voltage down detection circuit enable).
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5. Reset M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 5.0V 5.0V Vdet4 Vdet3r Vdet3 VCC Vdet3s VSS RESET Internal Reset Signal VC13 bit in VCR1 register Indefinite Set to “1” by program (reset level detect circuit enable) VC26 bit in VCR2 register (1) Indefinite VC27 bit in VCR2 register Indefinite Set to “1” by program (voltage down detect circuit enable) NOTES : 1. VC26 bit is invalid (the microcomputer is not reset even if input voltage of VCC pin becomes lower than Vdet3). Figure 5.5.3.
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5. Reset M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 5.5.1 Voltage Down Detection Interrupt If the D40 bit in the D4INT register is set to “1” (voltage down detection interrupt enabled), the voltage down detection interrupt request is generated when the voltage applied to the VCC pin crosses the Vdet4 voltage level. The voltage down detection interrupt shares the same interrupt vector with the watchdog timer interrupt and oscillation stop, re-oscillation detection interrupt.
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5. Reset M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Voltage down detection interrupt generation circuit DF1, DF0 00b The D42 bit is set to “0” (not detected) by program. the VC27 bit is set to “0” (voltage down detect circuit disabled), the D42 bit is set to “0”.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 5. Reset 5.5.2 Limitations on Exiting Stop Mode The voltage down detection interrupt is immediately generated and the microcomputer exits stop mode if the CM10 bit in the CM1 register is set to “1” under the conditions below.
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6. Processor Mode M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 6. Processor Mode The microcomputer supports single-chip mode only. Figures 6.1 and 6.2 show the associated registers. Processor Mode Register 0 (1) b7 b6 b5 b4 b3 0 0 0 0 b2 b1 b0 0 0 0 Symbol PM0 Bit Symbol Address 000416 After Reset 0016 Bit Name Function RW (b2-b0) Reserved bit Set to "0" RW PM03 Software reset bit The microcomputer is reset when this bit is set to "1". When read, its content is "0".
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6.
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6. Processor Mode M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) The internal bus consists of CPU bus, memory bus, and peripheral bus. Bus Interface Unit (BIU) is used to interfere with CPU, ROM/RAM, and perpheral functions by controling CPU bus, memory bus, and peripheral bus. Figure 6.3 shows the block diagram of the internal bus. ROM RAM CPU address bus CPU CPU data bus Memory address bus BIU Memory data bus DMAC Timer WDT ADC . . . .
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7. Clock Generation Circuit M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 7. Clock Generation Circuit The clock generation circuit contains four oscillator circuits as follows: (1) Main clock oscillation circuit (2) Sub clock oscillation circuit (3) On-chip oscillator (available at reset, oscillation stop detect function) (4) PLL frequency synthesizer Table 7.1 lists the clock generation circuit specifications. Figure 7.1 shows the clock generation circuit. Figures 7.2 to 7.
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7.
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7. Clock Generation Circuit M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) System clock control register 0 (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol CM0 Bit symbol Address 000616 After reset 010010002 (M16C/26A, M16C/26B) 011010002 (M16C/26T) Function Bit name CM00 CM01 CM02 CM03 Clock output function select bit RW RW Refer to Table 7.5.3.
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7.
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7.
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7.
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7. Clock Generation Circuit M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) PLL control register 0 b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 (1, 2) Symbol Address PLC0 001C16 Bit symbol PLC00 PLL multiplying factor (3) select bit PLC02 (b4) Function Bit name PLC01 (b3) After reset 0001 X0102 b2 b1b0 0 0 0: Do not set 0 0 1: Multiply by 2 0 1 0: Multiply by 4 0 1 1: 1 0 0: 1 0 1: Do not set 1 1 0: 1 1 1: RW RW RW Nothing is assigned. When write, set to "0".
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7. Clock Generation Circuit M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) The following describes the clocks generated by the clock generation circuit. 7.1 Main Clock The main clock is generated by the main clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks. The main clock oscillator circuit is configured by connecting a resonator between the XIN and XOUT pins.
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7. Clock Generation Circuit M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 7.2 Sub Clock The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for the CPU clock, as well as the timer A and timer B count sources. The sub clock oscillator circuit is configured by connecting a crystal resonator between the XCIN and XCOUT pins.
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7. Clock Generation Circuit M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 7.3 On-chip Oscillator Clock This clock is supplied by a on-chip oscillator. This clock is used as the clock source for the CPU and peripheral function clocks. In addition, if the PM22 bit in the PM2 register is “1” (on-chip oscillator clock for the watchdog timer count source), this clock is used as the count source for the watchdog timer (Refer to 10.1 Count source protective mode).
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) START Set the CM07 bit to “0” (main clock), the CM17 to CM16 bits to “002”(main clock undivided), and the CM06 bit to “0” (CM16 and CM17 bits enabled). (1) Set the PLC02 to PLC00 bits (multiplying factor). (To select a 16 MHz < PLL clock) Set the PM20 bit to “0” (2-wait states). Set the PLC07 bit to “1” (PLL operation). Wait until the PLL clock becomes stable (tsu(PLL)). Set the CM11 bit to “1” (PLL clock for the CPU clock source). END NOTE: 1.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 7. Clock Generation Circuit 7.5 CPU Clock and Peripheral Function Clock The CPU clock is used to operate the CPU and peripheral function clocks are used to operate the peripheral functions. 7.5.1 CPU Clock This is the operating clock for the CPU and watchdog timer. The clock source for the CPU clock can be chosen to be the main clock, sub clock, on-chip oscillator clock or the PLL clock.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 7. Clock Generation Circuit 7.6 Power Control There are three power control modes. For convenience’ sake, all modes other than wait and stop modes are referred to as normal operation mode here. 7.6.1 Normal Operation Mode Normal operation mode is further classified into seven modes. In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the CPU and the peripheral functions are operating.
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7. Clock Generation Circuit M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 7.6.1.6 On-chip Oscillator Mode The selected on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The on-chip oscillator clock is also the clock source for the peripheral function clocks. If the sub clock is on, fC32 can be used as the count source for timers A and B. The on-chip oscillator frequency can be selected ROCR3 to ROCR0 bits in ROCR register.
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7. Clock Generation Circuit M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 7.6.2.3 Pin Status During Wait Mode Table 7.6.2.3.1 lists pin status during wait mode. Table 7.6.2.3.1 Pin Status in Wait Mode Pin I/O ports When fC selected CLKOUT When f1, f8, f32 selected Status Retains status before wait mode Does not stop Does not stop when the CM02 bit is set to “0”. Retains status before wait mode when the CM02 bit is set to “1”. 7.6.2.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 7. Clock Generation Circuit 7.6.3 Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least amount of power is consumed in this mode. If the voltage applied to Vcc pin is VRAM or more, the internal RAM is retained. When applying 2.7 or less voltage to Vcc pin, make sure Vcc≥VRAM.
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7. Clock Generation Circuit M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Figure 7.6.1 shows the state transition from normal operation mode to stop mode and wait mode. Figure 7.6.1.1 shows the state transition in normal operation mode. Table 7.6.1 shows a state transition matrix describing allowed transition and setting. The vertical line shows current state and horizontal line shows state after transition.
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7.
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7. Clock Generation Circuit M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Table 7.6.1.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 7. Clock Generation Circuit 7.7 System Clock Protective Function When the main clock is selected for the CPU clock source, this function protects the clock from modifications in order to prevent the CPU clock from becoming halted by run-away.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 7. Clock Generation Circuit 7.8.1 Operation When the CM27 bit is set to "0" (Oscillation Stop Detection Reset) When main clock stop is detected when the CM20 bit is “1” (oscillation stop, re-oscillation detection function enabled), the microcomputer is initialized, coming to a halt (oscillation stop reset; refer to 4. SFR, 5. Reset). This status is reset with hardware reset 1 or hardware reset 2.
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7. Clock Generation Circuit M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 7.8.3 How to Use Oscillation Stop and Re-oscillation Detect Function • The oscillation stop and re-oscillation detect interrupt shares the vector with the watchdog timer interrupt. If the oscillation stop, re-oscillation detection and watchdog timer interrupts both are used, read the CM22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt.
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8. Protection M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 8. Protection Note The PRC3 bit in the PRCR register is not available in M16C/26T. In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Figure 8.1 shows the PRCR register. The following lists the registers protected by the PRCR register.
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9. Interrupt M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 9. Interrupt Note The 42-pin package does not use UART0 transmission interrupt and UART0 reception interrupt of peripheral function. M16C/26T does not use voltage down detection interrupt. 9.1 Type of Interrupts Figure 9.1.1 shows types of interrupts.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 9. Interrupt 9.1.1 Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. 9.1.1.1 Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction. 9.1.1.2 Overflow Interrupt An overflow interrupt occurs when executing the INTO instruction with the O flag set to “1” (the operation resulted in an overflow).
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 9. Interrupt 9.1.2 Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts. 9.1.2.1 Special Interrupts Special interrupts are non-maskable interrupts. _______ 9.1.2.1.1 NMI Interrupt _______ _______ An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details _______ _______ about the NMI interrupt, refer to the section 9.7 NMI Interrupt. ________ 9.1.
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9. Interrupt M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 9.2 Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt vector. Figure 9.2.1 shows the interrupt vector.
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9. Interrupt M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 9.2.2 Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector table area. Table 9.2.2.1 lists the relocatable vector tables. Setting an even address in the INTB register results in the interrupt sequence being executed faster than in the case of odd addresses. Table 9.2.2.1.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 9. Interrupt 9.3 Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to nonmaskable interrupts. Use the I flag in the FLG register, IPL, and the ILVL2 to ILVL0 bits in the each interrupt control register to enable/disable the maskable interrupts.
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9. Interrupt M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 9.3.1 I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (= enabled) enables the maskable interrupt. Setting the I flag to “0” (= disabled) disables all maskable interrupts. 9.3.2 IR Bit The IR bit is set to “1” (= interrupt requested) when an interrupt request is generated.
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9. Interrupt M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 9.4 Interrupt Sequence An interrupt sequence (the devicebehavior from the instant an interrupt is accepted to the instant the interrupt routine is executed) is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle.
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9. Interrupt M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 9.4.1 Interrupt Response Time Figure 9.4.1.1 shows the interrupt response time. The interrupt response or interrupt acknowledge time denotes the time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed. Specifically, it consists of the time from when an interrupt request is generated till when the instruction then executing is completed ((a) in Figure 9.4.1.
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9. Interrupt M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 9.4.3 Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure 9.4.3.1 shows the stack status before and after an interrupt request is accepted.
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9. Interrupt M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP(1), at the time of acceptance of an interrupt request, is even or odd. If the stack pointer (1) is even, the FLG register and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits at a time. Figure 9.4.3.2 shows the operation of the saving registers. NOTE: 1.
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9. Interrupt M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 9.4.4 Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine. Thereafter the CPU returns to the program which was being executed before accepting the interrupt request.
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9. Interrupt M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) ______ 9.6 INT Interrupt _______ INTi interrupt (i=0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the IFSRi bit in the IFSR register. ________ ________ ________ To use the INT4 interrupt, set the IFSR6 bit in the IFSR register to "1" (=INT4). To use the INT5 interrupt, set ________ the IFSR7 bit in the IFSR register to "1" (=INT5).
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9. Interrupt M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) ______ 9.7 NMI Interrupt _______ _______ An NMI interrupt request is generated when input on the NMI pin changes state from high to low, after the _______ ______ NMI interrupt was enabled by writing a “1” to PM24 bit in the PM2 register. The NMI interrupt is a nonmaskable interrupt, once it is enabled. _______ The input level of this NMI interrupt input pin can be read by accessing the P8_5 bit in the P8 register.
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9. Interrupt M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 9.9 Address Match Interrupt An address match interrupt request is generated immediately before executing the instruction at the address indicated by the RMADi register (i=0 to 1). Set the start address of any instruction in the RMADi register. Use the AIER register’s AIER0 and AIER1 bits to enable or disable the interrupt. Note that the address match interrupt is unaffected by the I flag and IPL.
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9. Interrupt M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Address match interrupt enable register b7 b6 b5 b4 b3 b2 b1 b0 Symbol AIER Bit symbol Address 0009 16 After reset XXXXXX00 2 Function RW AIER0 Address match interrupt 0 enable bit Bit name 0 : Interrupt disabled 1 : Interrupt enabled RW AIER1 Address match interrupt 1 enable bit 0 : Interrupt disabled 1 : Interrupt enabled RW (b7-b2) Nothing is assigned. When write, set to “0”. When read, their contents are indeterminate.
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10. Watchdog Timer M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 10. Watchdog Timer The watchdog timer is the function that detects when a program is out of control. Use the watchdog timer is recommended to improve reliability of the system. The watchdog timer contains a 15-bit counter which is decremented by the CPU clock that the prescaler divides.
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11. DMAC M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 11. DMAC Note Do not use UART0 transfer and UART0 reception interrupt request as a DMA request in the 42-pin package. The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention. Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit) data from the source address to the destination address. The DMAC uses the same data bus as used by the CPU.
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11. DMAC M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Table 11.1 DMAC Specifications Item No. of channels Transfer memory space Maximum No.
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11. DMAC M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) DMA0 request cause select register b7 b6 b5 b4 b3 b2 b1 Symbol DM0SL b0 Address 03B816 Bit symbol DSEL0 DSEL1 After reset 0016 Function Bit name DMA request cause select bit Refer to note RW RW RW DSEL2 RW DSEL3 RW (b5-b4) DMS Nothing is assigned. When write, set to “0”. When read, its content is “0”.
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11. DMAC M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) DMA1 request cause select register b7 b6 b5 b4 b3 b2 b1 Symbol DM1SL b0 Address 03BA16 DSEL1 DSEL2 Function Bit name Bit symbol DSEL0 After reset 0016 DMA request cause select bit RW Refer to note RW RW DSEL3 (b5-b4) DMS RW RW Nothing is assigned. When write, set to “0”. When read, its content is “0”.
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11. DMAC M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) DMAi source pointer (i = 0, 1) (1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol SAR0 SAR1 Address 002216 to 0020 16 003216 to 0030 16 Setting range RW 00000 16 to FFFFF 16 RW Function Set the source address of transfer After reset Indeterminate Indeterminate Nothing is assigned. When write, set “0”. When read, these contents are “0”. NOTE: 1.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 11. DMAC 11.1 Transfer Cycles The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus cycle. The number of read and write bus cycles is affected by the source and destination addresses of transfer. Furthermore, the bus cycle itself is extended by a software wait. 11.1.
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11. DMAC M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 11.2. DMA Transfer Cycles Any combination of even or odd transfer read and write adresses is possible. Table 11.2.1 shows the number of DMA transfer cycles. Table 11.2.2 shows the Coefficient j, k. The number of DMAC transfer cycles can be calculated as follows: No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k Table 11.2.
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11. DMAC M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 11.3 DMA Enable When a data transfer starts after setting the DMAE bit in DMiCON register (i = 0, 1) to “1” (enabled), the DMAC operates as follows: (1) Reload the forward address pointer with the SARi register value when the DSD bit in the DMiCON register is “1” (forward) or the DARi register value when the DAD bit in the DMiCON register is “1” (forward). (2) Reload the DMAi transfer counter with the DMAi transfer counter reload register value.
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11. DMAC M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 11.5 Channel Priority and DMA Transfer Timing If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are detected active in the same sampling period (one period from a falling edge to the next falling edge of CPU clock), the DMAS bit on each channel is set to “1” (DMA requested) at the same time. In this case, the DMA requests are arbitrated according to the channel priority, DMA0 > DMA1.
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12. Timer M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 12. Timer Note The TB2IN pin is not available in the 42-pin package. Do not use functions associated with the TB2IN pin. Eight 16-bit timers, each capable of operating independently of the others, can be classified by function as either timer A (five) and timer B (three). The count source for each timer acts as a clock, to control such timer operations as counting, reloading, etc. Figures 12.1 and 12.
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12. Timer M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 12.1 Timer A Figure 12.1.1 shows a block diagram of the timer A. Figures 12.1.2 to 12.1.4 show registers related to the timer A. The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the same function. Use the TMOD1 to TMOD0 bits in the TAiMR register (i = 0 to 4) to select the desired mode. • Timer mode: The timer counts an internal count source.
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12. Timer M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) One-shot start flag b7 b6 b5 b4 b3 b2 b1 Symbol ONSF b0 Bit symbol Address 038216 After reset 0016 Function RW The timer starts counting by setting this bit to “1” while the TMOD1 to TMOD0 bits in the TAiMR register (i = 0 to 4) is set to ‘10 2’ (= oneshot timer mode) and the MR2 bit in the TAiMR register is set to “0” (=TAiOS bit enabled). When read, its content is “0”.
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12. Timer M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 12.1.1. Timer Mode In timer mode, the timer counts a count source generated internally (see Table 12.1.1.1). Figure 1.2.1.1.1 shows TAiMR register in timer mode. Table 12.1.1.1.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 12. Timer 12.1.2. Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Timers A2, A3 and A4 can count two-phase external signals. Table 12.1.2.1 lists specifications in event counter mode (when not processing two-phase pulse signal). Table 12.1.2.2 lists specifications in event counter mode (when processing two-phase pulse signal with the timers A2, A3 and A4). Figure 12.1.2.
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12. Timer M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Table 12.1.2.2.
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12. Timer M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Timer Ai mode register (i=2 to 4) (When using two-phase pulse signal processing) b6 b5 b4 b3 b2 b1 b0 0 1 0 0 0 1 Symbol TA2MR to TA4MR Bit symbol TMOD0 Address 039816 to 039A 16 Function RW 0 1 : Event counter mode RW RW Bit name Operation mode select bit TMOD1 After reset 0016 b1 b0 MR0 To use two-phase pulse signal processing, set this bit to “0”. RW MR1 To use two-phase pulse signal processing, set this bit to “0”.
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12. Timer M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 12.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing This function initializes the timer count value to “0” by Z-phase (counter initialization) input during twophase pulse signal processing. This function can only be used in timer A3 event counter mode during two-phase pulse signal process_______ ing, free-running type, x4 processing, with Z-phase entered from the INT2 pin.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 12. Timer 12.1.3. One-shot Timer Mode In one-shot timer mode, the timer is activated only once by one trigger. (See Table 12.1.3.1.) When the trigger occurs, the timer starts up and continues operating for a given period. Figure 12.1.3.1 shows the TAiMR register in one-shot timer mode. Table 12.1.3.1.
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12. Timer M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 12.1.4. Pulse Width Modulation (PWM) Mode In PWM mode, the timer outputs pulses of a given width in succession (see Table 12.1.4.1). The counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 12.1.4.1 shows TAiMR register in pulse width modulation mode. Figures 12.1.4.2 and 12.1.4.3 show examples of how a 16-bit pulse width modulator operates and how an 8-bit pulse width modulator operates. Table 12.1.4.1.
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12. Timer M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 1 / f i X (2 16 – 1) Count source “H” Input signal to TAiIN pin “L” Trigger is not generated by this signal 1 / fj X n PWM pulse output from TA iOUT pin “H” IR bit in the TAiIC register “1” “L” “0” fj : Frequency of count source (f1, f 2, f8, f 32, fC32) i = 0 to 4 Set to “0” upon accepting an interrupt request or by writing in program NOTES: 1. n = 000016 to FFFE16. 2.
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12. Timer M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 12.2 Timer B Note The TB2IN pin for Timer B2 is not available in 42-pin package. [Precautions when using Timer B2] • Event Counter Mode The external input signals cannot be counted. Set the TCK1 bit in the TB2MR register to “1” when using the Event Count Mode. • Pulse Period/Pulse Width Measurement Mode This mode connot be used. Figure 12.2.1 shows a block diagram of the timer B. Figures 12.2.2 and 12.2.3 show registers related to the timer B.
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12. Timer M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 12.2.1 Timer Mode In timer mode, the timer counts a count source generated internally (see Table 12.2.1.1). Figure 12.2.1.1 shows TBiMR register in timer mode. Table 12.2.1.
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12. Timer M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 12.2.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers (see Table 12.2.2.1) . Figure 12.2.2.1 shows TBiMR register in event counter mode. Table 12.2.2.
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12. Timer M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 12.2.3 Pulse Period and Pulse Width Measurement Mode In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an external signal (see Table 12.2.3.1). Figure 12.2.3.1 shows TBiMR register in pulse period and pulse width measurement mode. Figure 12.2.3.2 shows the operation timing when measuring a pulse period. Figure 12.2.3.3 shows the operation timing when measuring a pulse width. Table 12.2.3.
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12. Timer M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Count source “H” Measurement pulse Reload register transfer timing “L” Transfer (indeterminate value) Transfer (measured value) counter (1) (1) (2) Timing at which counter reaches “0000 16” “1” TBiS bit “0” IR bit in the TBiIC register “1” MR3 bit in theTBiMR register “1” “0” Set to “0” upon accepting an interrupt request or by writing in program “0” The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.
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12. Timer M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 12.2.4 A/D Trigger Mode A/D trigger mode is used as conversion start trigger for A/D converter in simultaneous sample sweep mode of A/D conversion or delayed trigger mode 0. This mode is used as conversion start trigger of A/D converter. A/D trigger mode is used in Timer B0 and Timer B1. In this mode, the timer starts counting by one trigger until the count value becomes 000016. Figure 12.2.4.
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12. Timer M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Timer Bi mode register (i= 0 to 1) b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol TB0MR to TB1MR Bit symbol TMOD0 Address 039B16 to 039C 16 Bit name Function Operation Mode Select Bit TMOD1 MR0 After reset 00XX0000 2 RW RW b1 b0 0 0 : Timer mode or A/D trigger mode RW RW Invalid in A/D trigger mode Either "0" or "1" is enabled MR1 RW TB0MR register Set to “0” in A/D trigger mode MR2 RW TB1MR register Nothing is assigned.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 12. Timer 12.3 Three-phase Motor Control Timer Function Timers A1, A2, A4 and B2 can be used to output three-phase motor drive waveforms. Table 12.3.1 lists the specifications of the three-phase motor control timer function. Figure 12.3.1 shows the block diagram for three-phase motor control timer function. Also, the related registers are shown on Figure 12.3.2 to Figure 12.3.8. Table 12.3.1.
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Rev. 2.00 Feb.15, 2007 REJ09B0202-0200 page 118 of 329 T Q INV11 (One-shot timer mode) Timer A4 counter Reload Figure 12.3.1.
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12. Timer M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Three-phase output buffer register(i=0,1) (1) b7 b5 b4 b3 b2 b1 b0 Symbol Address When reset IDB0 034A16 IDB1 034B16 001111112 001111112 Bit symbol Bit name Function DUi U phase output buffer i DUBi U phase output buffer i RW Write the output level 0: Active level 1: Inactive level RW RW When read, these bits show the three-phase output shift register value.
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12. Timer M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Timer B2 register (1) (b15) b7 (b8) b0 b7 b0 Symbol TB2 Address 039516 to 039416 After reset Indeterminate Setting range Function Divide the count source by n + 1 where n = set value. Timer A1, A2 and A4 are started at every occurrence of underflow. RW 000016 to FFFF16 RW NOTE: 1. The register must be accessed in 16 bit units.
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12. Timer M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) The three-phase motor control timer function is enabled by setting the INV02 bit in the VC0 register to “1”. When this function is on, timer B2 is used to control the carrier wave, and timers A4, A1 and A2 are used to __ ___ ___ control three-phase PWM outputs (U, U, V, V, W and W). The dead time is controlled by a dedicated deadtime timer. Figure 12.3.9 shows the example of triangular modulation waveform, and Figure 12.3.
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12. Timer M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Carrier wave: sawtooth waveform Carrier wave Signal wave Timer B2 Start trigger signal for timer A4* Timer A4 one-shot pulse* Rewriting IDB0, IDB1 registers Transfer to three-phase output shift register U phase output signal * U phase output signal * INV14 = 0 (“L” active) U phase Dead time U phase INV14 = 1 (“H” active) U phase Dead time U phase * Internal signals. See the block diagram of the three-phase motor control timer function.
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12. Timer M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 12.3.1 Position-data-retain Function This function is used to retain the position data synchronously with the three-phase waveform output.There are three position-data input pins for U, V, and W phases. A trigger to retain the position data (hereafter, this trigger is referred to as "retain trigger") can be selected by the retain-trigger polarity select bit(bit 3 of the position-data-retain function control register, at address 034E16).
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12. Timer M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 12.3.1.2 Position-data-retain Function Control Register Figure 12.3.1.2.1 shows the structure of the position-data-retain function contol register.
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12. Timer M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 12.3.2 Three-phase/Port Output Switch Function When the INVC03 bit in the INVC0 register set to “1”(Timer output enabled for three-phase motor control) and setting the PFCi (i=0 to 5) in the PFCR register to “0”(I/O port), the three-phase PWM output pin (U, __ __ ___ U, V, V, W and W) functions as I/O port. Each bit in the PFCi bits (i=0 to 5) is applicable for each one of three-phase PWM output pins. Figure 12.3.2.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 13. Serial I/O 13. Serial I/O Note UART0 is not available in the 42-pin package. Serial I/O is configured with three channels: UART0 to UART2. 13.1. UARTi (i=0 to 2) UARTi each have an exclusive timer to generate a transfer clock, so they operate independently of each other. Figure 13.1.1 shows the block diagram of UARTi. Figures 13.1.2 and 13.1.3 shows the block diagram of the UARTi transmit/receive.
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13. Serial I/O M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) UARTi Transmit Buffer Register (i=0 to 2)(1) (b15) b7 (b8) b0 b7 b0 Symbol U0TB U1TB U2TB Address 03A3 16-03A2 16 03AB 16-03AA 16 037B 16-037A 16 After Reset Indeterminate Indeterminate Indeterminate Function RW Transmit data WO Nothing is assigned. When write, set to "0". When read, its content is indeterminate. NOTES: 1. Use MOV instruction to write to this register.
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13. Serial I/O M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) UART2 special mode register 3 b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR3 Bit symbol After reset 000X0X0X 2 Function Bit name RW Nothing is assigned. When write, set “0”. When read, its content is indeterminate. (b0) Clock phase set bit CKPH 0 : Without clock delay 1 : With clock delay RW Nothing is assigned. When write, set “0”. When read, its content is indeterminate.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 13. Serial I/O 13.1.1. Clock Synchronous serial I/O Mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 13.1.1.1 lists the specifications of the clock synchronous serial I/O mode. Table 13.1.1.2 lists the registers used in clock synchronous serial I/O mode and the register values set. Table 13.1.1.1.
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13. Serial I/O M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Table 13.1.1. 2.
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13. Serial I/O M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Table 13.1.1.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table 13.3 shows pin functions for the case where the multiple transfer clock output pin select function is deselected. Table 13.1.1.4 lists the P64 pin functions during clock synchronous serial I/O mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an “H”.
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13. Serial I/O M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 13.1.1.1 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode, follow the procedures below.
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13. Serial I/O M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 13.1.1.3 LSB First/MSB First Select Function Use the UFORM bit in the UiC0 register (i = 0 to 2) to select the transfer format. Figure 13.1.1.3.1 shows the transfer format.
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13. Serial I/O M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 13.1.1.5 Serial data logic switch function (UART2) When the U2LCH bit in the U2C1 register is set to "1" (reverse), the data written to the U2TB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the U2RB register. Figure 13.1.1.4.1 shows serial data logic.
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13. Serial I/O M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) _______ _______ 13.1.1.7 CTS/RTS separate function (UART0) _______ _______ _______ _______ This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0 from the P64 pin. To use this function, set the register bits as shown below.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 13. Serial I/O 13.1.2. Clock Asynchronous Serial I/O (UART) Mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Tables 13.1.2.1 lists the specifications of the UART mode. Table 13.1.2.1.
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13. Serial I/O M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Table 13.1.2.2.
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13. Serial I/O M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Table 13.1.2.3 lists the functions of the input/output pins during UART mode. Table 13.1.2.4 lists the P64 pin functions during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an “H”. (If the N-channel open-drain output is selected, this pin is in a high-impedance state.) Table 13.1.2.3.
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13. Serial I/O M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) • Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) The transfer clock stops momentarily as CTSi is “H” when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTSi changes to “L”.
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13.
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13. Serial I/O M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 13.1.2.2. Counter Measure for Communication Error If a communication error occurs while transmitting or receiving in UART mode, follow the procedure below.
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13. Serial I/O M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 13.1.2.4. Serial Data Logic Switching Function (UART2) The data written to the U2TB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the U2RB register. Figure 13.1.2.4.1 shows serial data logic.
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13. Serial I/O M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) _______ _______ 13.1.2.6. CTS/RTS Separate Function (UART0) _______ _______ _______ _______ This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0 from the P64 pin. To use this function, set the register bits as shown below.
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13. Serial I/O M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 13.1.3 Special Mode 1 (I2C bus mode)(UART2) I2C bus mode is provided for use as a simplified I2C bus interface compatible mode. Table 13.1.3.1 lists the specifications of the I2C bus mode. Table 13.1.3.2 and 13.1.3.3 list the registers used in the I2C bus mode and the register values set. Table 13.1.3.4 lists the I2C bus mode fuctions. Figure 13.1.3.1 shows the block diagram for I2C bus mode. Figure 13.1.3.2 shows SCL2 timing.
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13.
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13. Serial I/O M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Table 13.1.3.2.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 13. Serial I/O Table 13.1.3.3.
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13. Serial I/O M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Table 13.1.3.4. I2C bus Mode Functions Clock synchronous serial I/O I2C bus mode (SMD2 to SMD0 = 0102 , IICM = 1) mode (SMD2 to SMD0 = 0012, IICM2 = 0 IICM2 = 1 IICM = 0) (NACK/ACK interrupt) (UART transmit/ receive interrupt) CKPH = 1 CKPH = 1 CKPH = 0 CKPH = 0 (Clock delay) (No clock delay) (Clock delay) (No clock delay) Function Factor of interrupt number 10 (1) (Refer to Fig.13.1.3.2.) Factor of interrupt number 15 (1) (Refer to Fig.13.1.
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13.
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13. Serial I/O M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 13.1.3.1 Detection of Start and Stop Condition Whether a start or a stop condition has been detected is determined. A start condition-detected interrupt request is generated when the SDA2 pin changes state from high to low while the SCL2 pin is in the high state. A stop condition-detected interrupt request is generated when the SDA2 pin changes state from low to high while the SCL2 pin is in the high state.
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13. Serial I/O M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Table 13.1.3.2.1.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 13. Serial I/O 13.1.3.4 Transfer Clock Data is transmitted/received using a transfer clock like the one shown in Figure 13.1.3.2.1. The CSC bit in the U2SMR2 register is used to synchronize the internally generated clock (internal SCL2) and an external clock supplied to the SCL2 pin.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 13. Serial I/O 13.1.3.7 ACK and NACK If the STSPSEL bit in the U2SMR4 register is set to “0” (start and stop conditions not generated) and the ACKC bit in the U2SMR4 register is set to “1” (ACK data output), the value of the ACKD bit in the U2SMR4 register is output from the SDA2 pin. If the IICM2 bit is set to "0", a NACK interrupt request is generated if the SDA2 pin remains high at the rising edge of the 9th bit of transmit clock pulse.
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13. Serial I/O M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 13.1.4 Special Mode 2 (UART2) Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are selectable. Table 13.1.4.1 lists the specifications of Special Mode 2. Table 13.1.4.2 lists the registers used in Special Mode 2 and the register values set. Figure 13.1.4.1 shows communication control example for Special Mode 2. Table 13.1.4.1.
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13. Serial I/O M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) P13 P12 P93 P72(CLK2) P72(CLK2) P71(RxD2) P71(RxD2) P70(TxD2) P70(TxD2) Microcomputer (Master) Microcomputer (Slave) P93 P72(CLK2) P71(RxD2) P70(TxD2) Microcomputer (Slave) Figure 13.1.4.1. Serial Bus Communication Control Example (UART2) Rev. 2.00 Feb.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 13. Serial I/O Table 13.1.4.2.
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13. Serial I/O M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 13.1.4.1 Clock Phase Setting Function One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit in the U2SMR3 register and the CKPOL bit in the U2C0 register. Make sure the transfer clock polarity and phase are the same for the master and slave to communicate. 13.1.4.1.1 Master (Internal Clock) Figure 13.1.4.1.1.1 shows the transmission and reception timing in master (internal clock). 13.1.4.1.
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13. Serial I/O M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) "H" Slave control input "L" "H" Clock input (CKPOL=0, CKPH=0) "L" "H" Clock input (CKPOL=1, CKPH=0) "L" "H" Data output timing D0 "L" Data input timing D1 D2 D3 D4 D5 D6 D7 Indeterminate Figure 13.1.4.1.2.1.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 13. Serial I/O 13.1.5 Special Mode 3 (IE Bus mode )(UART2) In this mode, one bit of IE Bus is approximated with one byte of UART mode waveform. Table 13.1.5.1 lists the registers used in IE Bus mode and the register values set. Figure 13.1.5.1 shows the functions of bus collision detect function related bits. If the TxD2 pin output level and RxD2 pin input level do not match, a UART2 bus collision detect interrupt request is generated. Table 13.1.5.1.
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13. Serial I/O M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) (1) The ABSCS bit in the U2SMR register (bus collision detect sampling clock select) If ABSCS=0, bus collision is determined at the rising edge of the transfer clock Transfer clock ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP TxD2 RxD2 Input to TA0IN Timer A0 If ABSCS is set to "1", bus collision is determined when timer A0 (one-shot timer mode) underflows .
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 13. Serial I/O 13.1.6 Special Mode 4 (SIM Mode) (UART2) Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be implemented, and this mode allows output of a low from the TxD2 pin when a parity error is detected. Tables 13.1.6.1 lists the specifications of SIM mode. Table 13.1.6.2 lists the registers used in the SIM mode and the register values set. Table 13.1.6.1.
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13. Serial I/O M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Table 13.1.6.2.
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13.
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13. Serial I/O M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Figure 13.1.6.2 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply pull-up. Microcomputer SIM card TxD2 RxD2 Figure 13.1.6.2. SIM Interface Connection 13.1.6.1 Parity Error Signal Output The parity error signal is enabled by setting the U2ERE bit in the U2C1 register’ to “1”. • When receiving The parity error signal is output when a parity error is detected while receiving data.
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13. Serial I/O M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 13.1.6.2 Format • Direct Format Set the PRY bit in the U2MR register to “1”, the UFORM bit in the U2C0 register to “0” and the U2LCH bit in the U2C1 register to “0”. • Inverse Format Set the PRY bit to “0”, UFORM bit to “1” and U2LCH bit to “1”. Figure 13.1.6.2.1 shows the SIM interface format.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 14. A/D Converter 14. A/D Converter Note P92 and P93 (AN32, AN24) are not available in the 42-pin package. Do not use P92 and P93 (AN32, AN24) as analog input pins in the 42-pin package. The microcomputer contains one A/D converter circuit based on 10-bit successive approximation method configured with a capacitive-coupling amplifier. The analog inputs share the pins with P100 to P107 (AN0 to ___________ AN7), P90 to P93 (AN30 to AN32, AN24).
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14.
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14.
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14.
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14. A/D Converter M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) A/D conversion status register 0 (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADSTAT0 Bit symbol ADERR0 ADERR1 (b2) Address After reset 03D316 0016 Bit name AN1 Trigger Status Flag Conversion Termination Flag Function RW 0 : AN1 trigger did not occur during AN0 conversion 1 : AN1 trigger occured during AN0 conversion RW 0 : Conversion not terminated 1 : Conversion terminated by Timer B0 underflow RW Nothing is assigned.
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14.
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14. A/D Converter M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 14.1 Operation Modes 14.1.1 One-Shot Mode In one-shot mode, analog voltage applied to a selected pin is once converted to a digital code. Table 14.1.1.1 shows the one-shot mode specifications. Figure 14.1.1.1 shows the operation example in oneshot mode. Figure 14.1.1.2 shows the ADCON0 to ADCON2 registers in one-shot mode. Table 14.1.1.
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14.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 14. A/D Converter 14.1.2 Repeat mode In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table 14.1.2.1 shows the repeat mode specifications. Figure 14.1.2.1 shows the operation example in repeat mode. Figure 14.1.2.2 shows the ADCON0 to ADCON2 registers in repeat mode. Table 14.1.2.
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14.
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14. A/D Converter M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 14.1.3 Single Sweep Mode In single sweep mode, analog voltages applied to the selected pins are converted one-by-one to a digital code. Table 14.1.3.1 shows the single sweep mode specifications. Figure 14.1.3.1 shows the operation example in single sweep mode. Figure 14.1.3.2 shows the ADCON0 to ADCON2 registers in single sweep mode. Table 14.1.3.
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14.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 14. A/D Converter 14.1.4 Repeat Sweep Mode 0 In repeat sweep mode 0, analog voltages applied to the selected pins are repeatedly converted to a digital code. Table 14.1.4.1 shows the repeat sweep mode 0 specifications. Figure 14.1.4.1 shows the operation example in repeat sweep mode 0. Figure 14.1.4.2 shows the ADCON0 to ADCON2 registers in repeat sweep mode 0. Table 14.1.4.
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14.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 14. A/D Converter 14.1.5 Repeat Sweep Mode 1 In repeat sweep mode 1, analog voltages applied to the all selected pins are converted to a digital code, with mainly used in the selected pins. Table 14.1.5.1 shows the repeat sweep mode 1 specifications. Figure 14.1.5.1 shows the operation example in repeat sweep mode 1. Figure 14.1.5.2 shows the ADCON0 to ADCON2 registers in repeat sweep mode 1. Table 14.1.5.
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14.
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14. A/D Converter M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 14.1.6 Simultaneous Sample Sweep Mode In simultaneous sample sweep mode, analog voltages applied to the selected pins are converted one-byone to a digital code. At this time, the input voltage of AN0 and AN1 are sampled simultaneously using two circuits of sample and hold circuit. Table 14.1.6.1 shows the simultaneous sample sweep mode specifications. Figure 14.1.6.1 shows the operation example in simultaneous sample sweep mode. Figure 14.1.
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14.
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14. A/D Converter M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) A/D trigger control register (1) b7 b6 b5 b4 b3 b2 0 b1 b0 Symbol 0 1 ADTRGCON Bit symbol Address After reset 03D2 16 0016 Bit name Function RW SSE A/D Operation Mode Select Bit 2 1 : Simultaneous sample sweep mode or delayed trigger mode 0, 1 RW DTE A/D Operation Mode Select Bit 3 0 : Any mode other than delayed trigger mode 0,1 RW AN0 Trigger Select Bit Refer to Table 14.1.6.
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14. A/D Converter M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 14.1.7 Delayed Trigger Mode 0 In delayed trigger mode 0, analog voltages applied to the selected pins are converted one-by-one to a digital code. The delayed trigger mode 0 used in combination with A/D trigger mode of Timer B. The Timer B0 underflow starts a single sweep conversion. After completing the AN0 pin conversion, the AN1 pin is not sampled and converted until the Timer B1 underflow is generated.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 14.
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14.
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14.
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14.
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14. A/D Converter M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) A/D trigger control register (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol 1 1 1 1 ADTRGCON Bit symbol Address After reset 03D2 16 0016 Bit name Function RW SSE A/D Operation Mode Select Bit 2 Simultaneous sample sweep mode or delayed trigger mode 0,1 DTE A/D Operation Mode Select Bit 3 Delayed trigger mode 0, 1 AN0 Trigger Select Bit Refer to Table 14.1.7.
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14. A/D Converter M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 14.1.8 Delayed Trigger Mode 1 In delayed trigger mode 1, analog voltages applied to the selected pins are converted one-by-one to a digital code. When the input of the ADTRG pin (falling edge) changes state from “H” to “L”, a single sweep conversion is started. After completing the AN0 pin conversion, the AN1 pin is not sampled and converted until the second ADTRG pin falling edge is generated.
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14.
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14.
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14.
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14. A/D Converter M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) A/D control register 0 (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADCON0 0 0 0 1 1 1 Address 03D616 Bit symbol CH0 After reset 00000XXX 2 Bit name Function 1 1 1 : Set to "111b" in delayed trigger mode 1 RW RW CH1 RW CH2 MD0 RW b2 b1 b0 Analog Input Pin Select Bit MD1 A/D Operation Mode Select Bit 0 TRG Trigger Select Bit ADST CKS0 b4 b3 RW 0 0 : One-shot mode or delayed trigger mode 0,1 Refer to Table 14.1.8.
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14. A/D Converter M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) A/D trigger control register (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol 0 0 1 1 ADTRGCON Bit symbol Address After reset 03D2 16 0016 Bit name Function RW SSE A/D Operation Mode Select Bit 2 Simultaneous sample sweep mode or delayed trigger mode 0,1 DTE A/D Operation Mode Select Bit 3 Delayed trigger mode 0, 1 AN0 Trigger Select Bit Refer to Table 14.1.8.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 14. A/D Converter 14.2 Resolution Select Function The BITS bit in the ADCON1 register determines the resolution. When the BITS bit is set to “1” (10-bit precision), the A/D conversion result is stored into bits 0 to 9 in the A/D register i (i=0 to 7). When the BITS bit is set to “0” (8-bit precision), the A/D conversion result is stored into bits 0 to 7 in the ADi register. 14.
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14. A/D Converter M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 14.5 Output Impedance of Sensor under A/D Conversion To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 14.5.1 has to be completed within a specified period of time. T (sampling time) as the specified time.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 15. CRC Calculation Circuit 15. CRC Calculation Circuit The Cyclic Redundancy Check (CRC) operation detects an error in data blocks. The microcomputer uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) or CRC-16 (X16 + X15 + X2 + 1) to generate CRC code. The CRC code is a 16-bit code generated for a block of a given data length in multiples of bytes.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 15.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 15. CRC Calculation Circuit b15 b0 (1) Setting 000016 (initial value) CRD data register CRCD [03BD16, 03BC16] b7 b0 (2) Setting 0116 CRC input register CRCIN [03BE16] 2 cycles After CRC calculation is complete b0 b15 CRD data register CRCD [03BD16, 03BC16] 118916 Stores CRC code The code resulting from sending 0116 in LSB first mode is (10000 0000).
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 16. Programmable I/O Ports 16. Programmable I/O Ports Note P60 to P63, P92 and P93 are not available in the 42-pin package. The programmable input/output ports (hereafter referred to simply as “I/O ports”) consist of 39 lines P15 to P17, P6, P7, P8, P90 to P93, P10 for the 48-pin package, or 33 lines P15 to P17, P64 to P67, P7, P8, P90 to P91, P10 for the 42-pin package.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 16. Programmable I/O Ports 16.4 Port Control Register Figure 16.4.1 shows the port control register. When the P1 register is read after setting the PCR0 bit in the PCR register to “1”, the corresponding port latch can be read no matter how the PD1 register is set. 16.5 Pin Assignment Control register (PACR) Figure 16.5.1 shows the PACR. After reset set the PACR2 to PACR0 bit before you input and output it to each pin.
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16.
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16. Programmable I/O Ports M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Pull-up selection Direction register P70 to P73 "1" Output Port latch Data bus Switching between CMOS and Nch (1) Input to respective peripheral functions Pull-up selection Direction register P82 to P84 Data bus Port latch (1) Input to respective peripheral functions Pull-up selection Direction register P62, P66, P77 Data bus Port latch (1) Input to respective peripheral functions NOTE: 1.
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16. Programmable I/O Ports M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Pull-up selection Direction register P63, P67 “1” Output Port latch Data bus (1) Switching between CMOS and Nch Pull-up selection P85 NMI Enable Direction register Port latch Data bus (1) Digital Debounce NMI Interrupt Input NMI Enable SD Pull-up selection P91, P92, P104 to P107 Direction register Data bus Port latch (1) Analog input Input to respective peripheral functions NOTE: 1. symbolizes a parasitic diode.
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16. Programmable I/O Ports M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) P90 (inside dotted-line included) P93 (inside dotted-line not included) Data bus Pull-up selection Direction register 1 Port latch Output (1) Analog input Input to respective peripheral functions Pull-up selection Direction register P87 Data bus Port latch (1) fc Rf Pull-up selection Rd Direction register P86 Data bus Port latch (1) NOTE: 1. symbolizes a parasitic diode.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 16. Programmable I/O Ports CNVSS CNVSS signal input (1) RESET RESET signal input (1) NOTE: 1. symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed Vcc. Figure 16.5. I/O Pins Rev. 2.00 Feb.
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16.
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16.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 16. Programmable I/O Ports Pull-up control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR0 Address 03FC 16 Bit symbol (b2-b0) PU03 Bit name After reset 00 16 Function RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. P15 to P1 7 pull-up 0 : Not pulled high 1 : Pulled high (1) RW Nothing is assigned. In an attempt to write to these bits, write “0”.
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16. Programmable I/O Ports M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Port control register b7 b6 b5 b4 b3 b2 b1 b0 Symbpl PCR Address 03FF16 Bit symbol PCR0 Bit name Port P1 control bit After reset 0016 Function RW Operation performed when the P1 register is read 0: When the port is set for input, the input levels of P10 to P17 RW pins are read. When set for output, the port latch is read. 1: The port latch is read regardless of whether the port is set for input or output.
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16. Programmable I/O Ports M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) NMI Digital Debounce Register (1,2) b7 b0 Symbol NDDR Address 033E16 After Reset FF16 Function If the set value =n, - n = 0 to FE 16; a signal with pulse width, greater than (n+1)/f8, is input into NMI / SD - n = FF 16; the digital debounce filter is disabled and all signals are input Setting Range RW 0016 to FF 16 RW NOTES: 1.
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16. Programmable I/O Ports M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Digital Debounce Filter f8 Clock P85 / P17 Port In Signal Out Data Bus Reload Value (write) To NMI and SD / INT5 and INPC17 Count Value (read) Data Bus f8 Reload Value FF 03 Port In Signal Out Count Value 03 FF 1 02 01 03 3 2 4 FF Port In (continued) Signal Out (continued) Count Value (continued) 03 FF 02 01 6 00 03 FF 7 8 FF 02 9 1. (Condition after reset).
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16. Programmable I/O Ports M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Table 16.1. Unassigned Pin Handling in Single-chip Mode Pin name Ports P1, P6 to P10 Connection After setting for input mode, connect every pin to V SS via a resistor(pull-down); or after setting for output mode, leave these pins open. (1, 2, 4) XOUT (3) Open XIN Connect via resistor to V CC (pull-up) (5) AV CC Connect to V CC AV SS, VREF Connect to V SS NOTES: 1.
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17. Flash Memory Version M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 17. Flash Memory Version 17.1 Flash Memory Performance The flash memory version is functionally the same as the mask ROM version except that it internally contains flash memory. In the flash memory version, the flash memory can perform in three rewrite mode : CPU rewrite mode, standard serial I/O mode and parallel I/O mode. Table 17.1 shows the flash memory version specifications. (Refer to Table 1.1 or Table 1.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 17. Flash Memory Version Table 17.2.
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17. Flash Memory Version M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 17.2 Memory Map The flash memory contains the user ROM area and the boot ROM area (reserved area). Figures 17.2.1 to 17.2.3 show the flash memory block diagram. The user ROM area has space to store the microcomputer operation program in single-chip mode and a separate 2-Kbyte space as the block A and B. The user ROM area is divided into several blocks.
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17. Flash Memory Version M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 00F00016 00F7FF16 00F80016 00FFFF16 Block B :2K bytes (2) Block A :2K bytes (2) 0F400016 Block 3 : 16K bytes (5) 0F7FFF16 0F800016 Block 2 : 16K bytes (5) 0FBFFF16 0FC00016 NOTES: 1. To specify a block, use the maximum even address in the block. 2. Blocks A and B are enabled to use when the PM10 bit in the PM1 register is set to "1". 3.
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17. Flash Memory Version M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 00F00016 00F7FF16 00F80016 00FFFF16 Block B :2K bytes (2) Block A :2K bytes (2) 0FA00016 Block 2 : 8K bytes (5) 0FBFFF16 0FC00016 NOTES: 1. To specify a block, use the maximum even address in the block. 2. Blocks A and B are enabled to use when the PM10 bit in the PM1 register is set to "1". 3.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 17. Flash Memory Version 17.3 Functions To Prevent Flash Memory from Rewriting The flash memory has a built-in ROM code protect function for parallel I/O mode and a built-in ID code check function for standard input/output mode to prevent the flash memory from reading or rewriting. 17.3.1 ROM Code Protect Function The ROM code protect function disables reading or changing the contents of the on-chip flash memory in parallel I/O mode. Figure 17.3.1.
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17. Flash Memory Version M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) ROM Code Protect Control Address(5) b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 1 1 1 Symbol ROMCP Address 0FFFFF16 Bit Name Bit Symbol (b5-b0) ROMCP1 Factory Setting FF16 (4) Function Reserved Bit Set to 1 ROM Code Protect Level 1 Set Bit (1, 2, 3, 4) b7 b6 00: 01: Enables protect 10: 11: Disables protect } RW RW RW RW NOTES: 1.
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17. Flash Memory Version M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 17.4 CPU Rewrite Mode In CPU rewrite mode, the user ROM area can be rewritten when the CPU executes software commands. Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on-board without using a ROM programmer, etc. Verify the Program and the Block Erase commands are executed only on blocks in the user ROM area.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 17. Flash Memory Version 17.4.1 EW0 Mode The microcomputer enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to “1” (CPU rewrite mode enabled) and is ready to acknowledge the software commands. EW0 mode is selected by setting the FMR11 bit in the FMR1 register to “0”. When setting the FMR01 bit to “1”, set to “1” after first writing “0”. The software commands control programming and erasing.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 17. Flash Memory Version 17.5 Register Description Figure 17.5.1 shows the flash memory control register 0 and flash memory control register 1. Figure 17.5.2 shows the flash memory control register 4. 17.5.1 Flash memory control register 0 (FMR0) •FMR 00 Bit This bit indicates the operation status of the flash memory. The bit is “0” during programming, erasing, or erase-suspend mode; otherwise, the bit is “1”.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 17. Flash Memory Version 17.5.2 Flash memory control register 1 (FMR1) •FMR11 Bit EW1 mode is entered by setting the FMR11 bit to “1” (EW1 mode). This bit is enabled only when the FMR01 bit is “1”. •FMR16 Bit The combined setting of the FMR02 bit and the FMR16 bit enables to program and erase in the user ROM area. To set this bit to “1”, it is necessary to set to “1” after first setting to “0”. Set this bit to “0” by only writing “0”.
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17.
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17.
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17. Flash Memory Version M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Low power consumption mode program Transfer a low power internal consumption mode program to RAM area Jump to the low power consumption mode program transferred to internal RAM area. (In the following steps, use the low-power consumption mode program or internal RAM area) Set the FMR01 bit to “1” after setting “0” (CPU rewrite mode enabled) Set the FMSTP bit to “1” (flash memory stopped.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 17. Flash Memory Version 17.6 Precautions in CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. 17.6.1 Operation Speed When CPU clock source is the main clock, before entering CPU rewrite mode (EW0 or EW1 mode), select 10 MHz or below for CPU clock using the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 17. Flash Memory Version 17.6.6 DMA Transfer In EW1 mode, do not perform a DMA transfer while the FMR00 bit in the FMR0 register is set to “0”. (the auto-programming or auto-erasing duration ). 17.6.7 Writing Command and Data Write the command code and data to even addresses in the user ROM area. 17.6.8 Wait Mode When entering wait mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) before executing the WAIT instruction. 17.6.
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17. Flash Memory Version M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 17.7 Software Commands Read or write 16-bit commands and data from or to even addresses in the user ROM area. When writing a command code, 8 high-order bits (D15–D8) are ignored. Table 17.7.1.
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17. Flash Memory Version M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 17.7.3 Clear Status Register Command (5016) This command clears the status register to “0”. By writing ‘xx5016’ in the first bus cycle, and the FMR06 to FMR07 bits in the FMR0 register and SR4 to SR5 bits in the status register are set to “0”. 17.7.4 Program Command (4016) The program command writes 2-byte data to the flash memory.
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17. Flash Memory Version M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 17.7.5 Block Erase By writing ‘xx2016’ in the first bus cycle and ‘xxD016’ in the second bus cycle to the highest-order (even addresse of a block) and the auto-programming/erasing (erase and erase verify) start. The FMR00 bit in the FMR0 register indicates whether the auto-programming operation has been completed.
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17. Flash Memory Version M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 17.8 Status Register The status register indicates the operating status of the flash memory and whether an erasing or a programming operates normally and an error ends. The FMR00, FMR06, and FMR07 bits in the FMR0 register indicate the status of the status register. Table 17.8.1 shows the status register.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 17. Flash Memory Version 17.8.4 Full Status Check When an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to “1”, indicating occurrence of each specific error. Therefore, execution results can be verified by checking these status bits (full status check). Table 17.8.4.1 shows errors and the status of FMR0 register. Figure 17.8.4.1 shows a flow chart of the full status check and handling procedure for each error. Table 17.8.4.1.
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17. Flash Memory Version M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Full status check FMR06 =1 and FMR07=1? YES Command sequence error NO FMR07=0? NO Erase error YES FMR06=0? NO YES Program error (1) Execute the clear status register command and set the status flag to “0” whether the command is entered. (2) Reexecute the command after checking that it is entered correctly or the program command or the block erase command is not executed for the blocks which are protected.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 17. Flash Memory Version 17.9 Standard Serial I/O Mode In standard serial input/output mode, the user ROM area can be rewritten while the microcomputer is mounted on-board by using a serial programmer which is applicable for the M16C/26A group. For more information about serial programmers, contact the manufacturer of your serial programmer. For details on how to use the serial programmer, refer to the user’s manual included with your serial programmer.
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17. Flash Memory Version M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Table 17.9.1. Pin Functions (Flash Memory Standard Serial I/O Mode) Name Pin Description I/O Apply the voltage guaranteed for Program and Erase to Vcc pin and 0 V to Vss pin. VCC,V SS Power input CNV SS CNV SS I Connect to Vcc pin. RESET Reset input I Reset input pin. While RESET pin is "L" level, wait for td(ROC).
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17. Flash Memory Version M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Vss Vcc 1 42 2 41 3 40 4 39 5 38 6 37 7 8 (1) CE 9 RESET 10 Connect oscillator circuit (1) RP 36 M16C/26A Group (M16C/26A) (Flash memory version) PRSP0042GA-B (42P2R) 35 (1) 34 P16 33 11 32 12 31 13 30 14 29 15 28 16 27 17 26 18 25 19 24 20 23 21 22 BUSY SCLK RxD NOTE: 1. Set following either or both in serial I/O mode while the RESET pin is held “L”. ⋅ Connect the CE pin to VCC.
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17. Flash Memory Version TxD 26 25 RxD 27 28 29 30 31 32 33 34 35 36 P16 BUSY (1) SCLK M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 37 24 38 23 39 22 40 21 20 41 M16C/26A Group 42 43 44 45 19 (M16C/26A, M16C/26B, M16C/26T) (Flash memory version) PLQP0048KB-A (48P6Q) 18 17 16 12 11 10 9 8 7 6 5 4 13 3 14 48 2 15 47 1 46 Mode setup method Signal Value CNVss Vcc Reset Vss to Vcc RP (1) Vcc CE (1) Vss RESET Connect oscillator circuit NOTE: 1.
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17. Flash Memory Version M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 17.9.2 Example of Circuit Application in Standard Serial I/O Mode Figure 17.9.2.1 shows an example of a circuit application in standard serial I/O mode 1 and Figure 17.9.2.2 shows an example of a circuit application in standard serial I/O mode 2. Refer to the user's manual for a serial writer to handle pins controlled by the serial writer.
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17. Flash Memory Version M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Microcomputer SCLK TxD output TxD Monitor output BUSY RxD input RxD (1) P86(CE) (1) P16 CNVss P85(RP) (1) In this example, a selector controls the input voltage applied to CNVss to switch between single-chip mode and standard serial I/O mode. NOTE: 1. Set following either or both • Connect the CE pin to VCC • Connect the RP pin to VSS and the P16 pin to VCC Figure 17.9.2.2.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 17. Flash Memory Version 17.10 Parallel I/O Mode In parallel input/output mode, the user ROM can be rewritten using a parallel programmer which is applicable for the M16C/26A group. For more information about the parallel programmer, contact your parallel programmer manufacturer. For details on how to use the parallel programmer, refer to the user’s manual of the parallel programmer. 17.10.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 18. Electrical Characteristics (M16C/26A, M16C/26B) 18. Electrical Characteristics Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for electrical characteristics of V-ver. 18.1. M16C/26A, M16C/26B (Normal version) Table 18.1. Absolute Maximum Ratings Symbol Parameter Condition Value Unit VCC Supply Voltage VCC = AVCC -0.3 to 6.5 V AVCC Analog Supply Voltage VCC = AVCC -0.3 to 6.
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18. Electrical Characteristics (M16C/26A, M16C/26B) M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Table 18.2. Recommended Operating Conditions (1) Symbol VCC AVCC Supply Voltage Analog Supply Voltage VSS AVSS VIH Input High ("H") Voltage VIL Standard Parameter Min. 2 .7 Typ. Unit M a x. 5 .5 VCC V V Supply Voltage 0 V Analog Supply Voltage 0 P15 to P17, P60 to P67, P70 to P77, VCC V 0.8 VCC VCC V 0 0.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 18. Electrical Characteristics (M16C/26A, M16C/26B) Table 18.3. A /D Conversion Characteristics(1) Symbol Parameter Standard Measurement Condition Min. - Resolution Integral Nonlinearity Error INL 10 bit 8 bit - Absolute Accuracy Unit Typ. Max. VREF = VCC 10 Bits VREF = VCC = 5V ±3 LSB VREF = VCC = 3.3 V ±5 LSB VREF = VCC = 3.3 V, 5 V ±2 LSB VREF = VCC = 5 V ±3 LSB VREF = VCC = 3.3 V ±5 LSB VREF = VCC = 3.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 18. Electrical Characteristics (M16C/26A, M16C/26B) Table 18.4. Flash Memory Version Electrical Characteristic (1): Program Space and Data Space for U3 and U5, Program Space for U7 and U9 Symbol - Standard Parameter Min. Typ.(2) 100/1000(4, 11) Program and Erase Endurance(3) Unit Max. cycles - Word Program Time (VCC=5.0V, Topr=25° C) 75 600 µs - Block Erase Time (VCC=5.0V, Topr=25° C) 0.2 0.4 0.7 1.
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18. Electrical Characteristics (M16C/26A, M16C/26B) M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Table 18.6. Voltage Detection Circuit Electrical Characteristics (1, 3) Symbol Parameter Vdet4 Low Voltage Detection Voltage(1) Voltage(1) Standard Measurement Condition Vdet3 Reset Level Detection Vdet3s Low Voltage Reset Hold Voltage(2) Vdet3r Low Voltage Reset Release Voltage VCC=0.8 to 5.5V Unit Min. Typ. Max. 3. 2 3.8 4.45 V 2.3 2.8 3 .4 V 1.7 V 3.5 V 2.35 2.9 NOTES: 1.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 18. Electrical Characteristics (M16C/26A, M16C/26B) VCC = 5V Table 18.8. Electrical Characteristics (1) Symbol VOH VOH Parameter XOUT VOH Output High ("H") Voltage VOL XCOUT IOH = -5 mA IOH =-200 µA VCC-0.3 VCC High Power IOH = -1mA VCC-2.0 VCC Low Power IOH = -0.5mA VCC-2.0 VCC High Power No load applied 2.5 Low Power No load applied 1 .
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 18. Electrical Characteristics (M16C/26A, M16C/26B) VCC = 5V Table 18.9. Electrical Characteristics (2) Symbol ICC (1) Parameter Power Supply Current (VCC = 4.0 to 5.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 18. Electrical Characteristics (M16C/26A, M16C/26B) VCC = 5V Timing Requirements (VCC = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified) Table 18.10. External Clock Input (XIN input) Symbol Parameter Standard Min. Max.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 18. Electrical Characteristics (M16C/26A, M16C/26B) VCC = 5V Timing Requirements (VCC = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified) Table 18.11. Timer A Input (Counter Input in Event Counter Mode) Symbol Parameter tc(TA) TAiIN input cycle time tw(TAH) TAiIN input HIGH pulse width tw(TAL) Standard Min. Max. 100 TAiIN input LOW pulse width Unit ns 40 ns 40 ns Table 18.12.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 18. Electrical Characteristics (M16C/26A, M16C/26B) VCC = 5V Timing Requirements (VCC = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified) Table 18.17. Timer B Input (Counter Input in Event Counter Mode) Symbol Parameter tc(TB) TBiIN input cycle time (counted on one edge) Standard Min. Max.
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18. Electrical Characteristics (M16C/26A, M16C/26B) M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) VCC = 5V tc(CK) tw(CKH) CLKi tw(CKL) th(C–Q) TxDi td(C–Q) tsu(D–C) RxDi tw(INL) INTi input tw(INH) Figure 18.2. Timing Diagram (2) Rev. 2.00 Feb.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 18. Electrical Characteristics (M16C/26A, M16C/26B) VCC = 3V Table 18.23. Electrical Characteristics Symbol VOH (1) Parameter XOUT VOH Output High ("H") Voltage XCOUT IOH=-1mA High Power IOH=-0.1mA VCC-0.5 VCC Low Power IOH=-50µA VCC-0.5 VCC High Power No load applied 2.5 Low Power No load applied 1.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 18. Electrical Characteristics (M16C/26A, M16C/26B) VCC = 3V Table 18.24. Electrical Characteristics (2) (1) Symbol ICC Parameter Power Supply Current (VCC = 2.7 to 3.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 18. Electrical Characteristics (M16C/26A, M16C/26B) VCC = 3V Timing Requirements (VCC = 3V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified) Table 18.25. External Clock Input (XIN input) Symbol Parameter Standard Min. Max.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 18. Electrical Characteristics (M16C/26A, M16C/26B) VCC = 3V Timing Requirements (VCC = 3V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified) Table 18.26. Timer A Input (Counter Input in Event Counter Mode) Symbol Parameter tc(TA) TAiIN input cycle time tw(TAH) TAiIN input HIGH pulse width tw(TAL) TAiIN input LOW pulse width Standard Min. Max. 150 60 60 Unit ns ns ns Table 18.27.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 18. Electrical Characteristics (M16C/26A, M16C/26B) VCC = 3V Timing Requirements (VCC = 3V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified) Table 18.32.
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18. Electrical Characteristics (M16C/26A, M16C/26B) M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) VCC = 3V tc(CK) tw(CKH) CLKi tw(CKL) th(C–Q) TxDi td(C–Q) tsu(D–C) RxDi tw(INL) INTi input tw(INH) Figure 18.4. Timing Diagram (2) Rev. 2.00 Feb.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 18. Electrical Characteristics (M16C/26T) 18.2. M16C/26T (T version) Table 18.38. Absolute Maximum Ratings Symbol VCC Parameter Supply Voltage AVCC Analog Supply Voltage VI Input Voltage Condition Value Unit VCC = AVCC -0.3 to 6.5 V VCC = AVCC -0.3 to 6.5 V -0.3 to VCC+0.3 V -0.3 to VCC+0.
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18. Electrical Characteristics (M16C/26T) M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Table 18.39. Recommended Operating Conditions (1) Symbol Standard Parameter Min. 3.0 Typ. Max. 5.5 Unit VCC AVCC Supply Voltage Analog Supply Voltage VSS Supply Voltage 0 V AVSS Analog Supply Voltage 0 V VIH Input High ("H") Voltage VIL Input Low ("L") Voltage VCC P15 to P17, P60 to P67, P70 to P77, P80 to P87, P90 to P93, P100 to P107 0.
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18. Electrical Characteristics (M16C/26T) M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Table 18.40. A/D Conversion Characteristics (1) Symbol Parameter Standard Measurement Condition Min. - Resolution Integral Nonlinearity Error INL 10 bit 8 bit - Absolute Accuracy Typ. Unit Max. VREF = VCC 10 Bits VREF = VCC = 5 V ±3 LSB VREF = VCC = 3.3 V ±5 LSB VREF = VCC = 3.3 V, 5 V ±2 LSB VREF = VCC = 5 V ±3 LSB VREF = VCC = 3.3 V ±5 LSB VREF = VCC = 3.
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18. Electrical Characteristics (M16C/26T) M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Table 18.41. Flash Memory Version Electrical Characteristics (1): Program Space and Data Space for U3, Program Space for U7 Symbol Standard Parameter Min. Typ.(2) ( 4 , 1 100/1000 1) Max. Unit - Program and Erase Endurance(3) - Word Program Time (VCC = 5.0 V, Topr = 25° C) 75 600 µs - Block Erase Time (VCC = 5.0 V, Topr = 25° C) 0.2 0.4 0.7 1.
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18. Electrical Characteristics (M16C/26T) M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Table 18.43. Power Supply Circuit Timing Characteristics Symbol Parameter Standard Measurement Condition Min. td(P-R) Wait Time to Stabilize Internal Supply Voltage when Power-on STOP Release Time(1) td(W-S) Low Power Dissipation Mode Wait Mode Release Time td(P-R) VCC = 3.0 to 5.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 18. Electrical Characteristics (M16C/26T) VCC = 5V Table 18.44. Electrical Characteristics Symbol VOH VOH (1) Parameter Output High P15 ("H") Voltage P80 Output High P15 ("H") Voltage P80 to P17, P60 to P87, P90 to P17, P60 to P87, P90 XOUT VOH Output High ("H") Voltage VOL Output Low P15 ("L") Voltage P80 Output Low P15 ("L") Voltage P80 XCOUT Min. IOH = -5 mA IOH = -200 µA VCC-0.3 VCC High Power IOH = -1 mA VCC-2.0 VCC Low Power IOH = -0.
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18. Electrical Characteristics (M16C/26T) M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) VCC = 5V Table 18.45. Electrical Characteristics (2) (1) Symbol ICC Parameter Measurement Condition Power Supply Output pins are Flash memory Current left open and (VCC=4.0 to 5.5V) other pins are connected to VSS Flash memory program Flash memory erase Flash memory f(BCLK) = 20 MHz, Main clock, no division On-chip oscillator operates, f2(ROC) selected, f(BCLK) = 1 MHz f(BCLK) = 10 MHz, Vcc = 5.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 18. Electrical Characteristics (M16C/26T) VCC = 5V Timing Requirements (VCC = 5V, VSS = 0V, at Topr = – 40 to 85oC unless otherwise specified) Table 18.46. External Clock Input (XIN input) Symbol tc tw(H) tw(L) tr tf Parameter External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time Rev. 2.00 Feb.15, 2007 REJ09B0202-0200 page 287 of 329 Standard Min. Max.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 18. Electrical Characteristics (M16C/26T) VCC = 5V Timing Requirements (VCC = 5V, VSS = 0V, at Topr = – 40 to 85oC unless otherwise specified) Table 18.47. Timer A Input (Counter Input in Event Counter Mode) Symbol Parameter tc(TA) TAiIN input cycle time tw(TAH) TAiIN input HIGH pulse width tw(TAL) TAiIN input LOW pulse width Standard Min. Max. 100 40 40 Unit ns ns ns Table 18.48.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 18. Electrical Characteristics (M16C/26T) VCC = 5V Timing Requirements (VCC = 5V, VSS = 0V, at Topr = – 40 to 85oC unless otherwise specified) Table 18.53. Timer B Input (Counter Input in Event Counter Mode) Symbol Parameter tc(TB) TBiIN input cycle time (counted on one edge) Standard Min. Max.
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18. Electrical Characteristics (M16C/26T) M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) VCC = 5V tc(CK) tw(CKH) CLKi tw(CKL) th(C–Q) TxDi td(C–Q) tsu(D–C) RxDi tw(INL) INTi input tw(INH) Figure 18.6. Timing Diagram (2) Rev. 2.00 Feb.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 18. Electrical Characteristics (M16C/26T) VCC = 3V Table 18.59. Electrical Characteristics (1) Symbol VOH Parameter XOUT VOH Output High ("H") Voltage XCOUT IOH = -1 mA High Power IOH = -0.1 mA VCC-0.5 VCC Low Power IOH = -50 µA VCC-0.5 VCC High Power No load applied 2.5 Low Power No load applied 1.
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18. Electrical Characteristics (M16C/26T) M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) VCC = 3V Table 18.60. Electrical Characteristics (2) Symbol ICC Parameter (1) Measurement Condition Power Supply Output pins are Flash memory Current left open and (VCC=3.0 to 3.6V) other pins are connected to VSS Flash memory program Flash memory erase Flash memory f(BCLK) = 10 MHz, Main clock, no division On-chip oscillator operates, f2(ROC) selected, f(BCLK) = 1 MHz Standard Min. Typ. 7 Unit Max.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 18. Electrical Characteristics (M16C/26T) VCC = 3V Timing Requirements (VCC = 3V, VSS = 0V, at Topr = – 40 to 85oC unless otherwise specified) Table 18.61. External Clock Input (XIN input) Symbol tc tw(H) tw(L) tr tf Parameter External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time Rev. 2.00 Feb.15, 2007 REJ09B0202-0200 page 294 of 329 Standard Min. Max.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 18. Electrical Characteristics (M16C/26T) VCC = 3V Timing Requirements (VCC = 3V, VSS = 0V, at Topr = – 40 to 85oC unless otherwise specified) Table 18.62. Timer A Input (Counter Input in Event Counter Mode) Symbol Parameter tc(TA) TAiIN input cycle time tw(TAH) TAiIN input HIGH pulse width tw(TAL) TAiIN input LOW pulse width Standard Min. Max. 150 60 60 Unit ns ns ns Table 18.63.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 18. Electrical Characteristics (M16C/26T) VCC = 3V Timing Requirements (VCC = 3V, VSS = 0V, at Topr = – 40 to 85oC unless otherwise specified) Table 18.68. Timer B Input (Counter Input in Event Counter Mode) Symbol Parameter Standard Min. Max.
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18.
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18. Electrical Characteristics (M16C/26T) M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) VCC = 3V tc(CK) tw(CKH) CLKi tw(CKL) th(C–Q) TxDi td(C–Q) tsu(D–C) RxDi tw(INL) INTi input tw(INH) Figure 18.8. Timing Diagram (2) Rev. 2.00 Feb.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 19. Usage Notes 19. Usage Notes 19.1 SFR 19.1.1 Precaution for 48-pin package Set the IFSR20 bit in the IFSR2A register to "1" after reset and set the PACR2 to PACR0 bits in the PACR register to "1002". 19.1.2 Precaution for 42-pin package Set the IFSR20 bit in the IFSR2A register to "1" after reset and set the PACR2 to PACR0 bits in the PACR register to "0012". 19.1.
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19. Usage Notes M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 19.2 PLL Frequency Synthesizer Stabilize supply voltage so that the standard of the power supply ripple is met. Standard Symbol Parameter f(ripple) Power supply ripple allowable frequency(VCC) Vp-p(ripple) Power supply ripple allowabled amplitude voltage VCC(|∆V/∆T|) Power supply ripple rising/falling gradient f(ripple) Power supply ripple allowable frequency (VCC) Vp-p(ripple) Power supply ripple allowable amplitude voltage Typ.
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19. Usage Notes M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 19.3 Power Control 1. When exiting stop mode by hardware reset, the device will startup using the on-chip oscillator. 2. Set the MR0 bit in the TAiMR register(i=0 to 4) to “0”(pulse is not output) to use the timer A to exit stop mode. 3. When entering wait mode, insert a JMP.B instruction before a WAIT instruction. Do not excute any instructions which can generate a write to RAM between the JMP.B and WAIT instructions.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 19. Usage Notes 5. Wait until the main clock oscillation stabilization time, before switching the CPU clock source to the main clock. Similarly, wait until the sub clock oscillates stably before switching the CPU clock source to the sub clock. 6. Suggestions to reduce power consumption (a) Ports The processor retains the state of each I/O port even when it goes to wait mode or to stop mode. A current flows in active I/O ports.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 19. Usage Notes 19.4 Protect Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to “0” (write protected). The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2 bit to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in which the PRC2 bit is set to “1” and the next instruction. Rev. 2.00 Feb.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 19. Usage Notes 19.5 Interrupts 19.5.1 Reading address 0000016 Do not read the address 0000016 in a program. When a maskable interrupt request is accepted, the CPU reads interrupt information (interrupt number and interrupt request priority level) from the address 0000016 during the interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to “0”.
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19. Usage Notes M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Changing the interrupt source Disable interrupts (2, 3) Change the interrupt generate factor (including a mode change of peripheral function) Use the MOV instruction to clear the IR bit to “0” (interrupt not requested) (3) Enable interrupts (2, 3) End of change IR bit: A bit in the interrupt control register for the interrupt whose interrupt generate factor is to be changed NOTES: 1. The above settings must be executed individually.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 19. Usage Notes 19.5.6 Rewrite the Interrupt Control Register (1) The interrupt control register for any interrupt should be modified in places where no requests for that interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control register. (2) To rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with the instruction to be used.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 19. Usage Notes 19.6 DMAC 19.6.1 Write to DMAE Bit in DMiCON Register When both of the conditions below are met, follow the steps below. Conditions • The DMAE bit is set to “1” again while it remains set (DMAi is in an active state). • A DMA request may occur simultaneously when the DMAE bit is being written. Step 1: Write “1” to the DMAE bit and DMAS bit in DMiCON register simultaneously(*1).
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 19. Usage Notes 19.7 Timer 19.7.1 Timer A 19.7.1.1 Timer A (Timer Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to “1” (count starts). Always make sure the TAiMR register is modified while the TAiS bit remains “0” (count stops) regardless whether after reset or not. 2.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 19. Usage Notes 19.7.1.3 Timer A (One-shot Timer Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to “1” (count starts).
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 19. Usage Notes 19.7.1.4 Timer A (Pulse Width Modulation Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to “1” (count starts).
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 19. Usage Notes 19.7.2 Timer B 19.7.2.1 Timer B (Timer Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i = 0 to 2) register and TBi register before setting the TBiS bit in the TABSR register to “1” (count starts). Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops) regardless whether after reset or not. 2.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 19. Usage Notes 19.7.2.3 Timer B (Pulse Period/pulse Width Measurement Mode) 1. The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR (i = 0 to 2) register before setting the TBiS bit in the TABSR register to “1” (count starts). Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops) regardless whether after reset or not.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 19. Usage Notes 19.8 Serial I/O 19.8.1 Clock-Synchronous Serial I/O 19.8.1.1 Transmission/reception _______ ________ 1. With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes to “L” when the data-receivable status becomes ready, which informs the transmission side ________ that the reception has become ready. The output level of the RTSi pin goes to “H” when reception ________ ________ starts.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 19. Usage Notes 19.8.2 Serial I/O (UART Mode) 19.8.1.1 Special Mode 1 (I2C bus Mode) When generating start, stop and restart conditions, set the STSPSEL bit in the U2SMR4 register to “0” and wait for more than half cycle of the transfer clock before setting each condition generate bit (STAREQ, RSTAREQ and STPREQ) from “0” to “1”. 19.8.1.
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19. Usage Notes M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 19.9 A/D Converter 1. Set ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A/D conversion is stopped (before a trigger occurs). 2. When the VCUT bit in the ADCON1 register is changed from “0” (Vref not connected) to “1” (VREF connected), start A/D conversion after waiting 1 µs or longer. 3.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 19. Usage Notes 8. If the CPU reads the A/D register i (i = 0 to 7) at the same time the conversion result is stored in the A/ D register i after completion of A/D conversion, an incorrect value may be stored in the A/D register i. This problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for CPU clock.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 19. Usage Notes 19.10 Programmable I/O Ports _____ 1. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to “1” _____ (three-phase output forcible cutoff by input on SD pin enabled), the P72 to P75, P80 and P81 pins go to a high-impedance state. 2. The input threshold voltage of pins differs between programmable input/output ports and peripheral functions.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 19. Usage Notes 19.11 Electric Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers Flash memory version and mask ROM version may have different characteristics, operating margin, noise tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout pattern, etc. When switching to the mask ROM version, conduct equivalent tests as system evaluation tests conducted in the flash memory version.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 19. Usage Notes 19.12 Mask ROM Version 19.12.1 Internal ROM area When using the masked ROM version, write nothing to internal ROM area. Writing to the area may increase power consumption. 19.12.2 Reserve bit The b3 to b0 in address 0FFFFF16 are reserved bits. Set these bits to “11112”. Rev. 2.00 Feb.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 19. Usage Notes 19.13 Flash Memory Version 19.13.1 Functions to Inhibit Rewriting Flash Memory ID codes are stored in addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. If wrong data is written to these addresses, the flash memory cannot be read or written in standard serial I/O mode. The ROMCP register is mapped in address 0FFFFF16.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 19. Usage Notes 19.13.9 Interrupts EW0 Mode • Any interrupt which has a vector in the variable vector table can be used, providing that its vector is transferred into the RAM area. _______ • The NMI and watchdog timer interrupts can be used because the FMR0 register and FMR1 register are initialized when one of those interrupts occurs. The jump addresses for those interrupt service routines should be set in the fixed vector table.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 19. Usage Notes 19.13.14 Definition of Programming/Erasure Times "Number of programs and erasure" refers to the number of erasure per block. If the number of program and erasure is n (n=100 1,000 10,000) each block can be erased n times. For example, if a 2K byte block A is erased after writing 1 word data 1024 times, each to a different address, this is counted as one program and erasure.
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19. Usage Notes M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 19.14 Noise Connect a bypass capacitor (approximately 0.1µF) across the VCC and VSS pins using the shortest and thicker possible wiring. Figure 19.4 shows the bypass capacitor connection. M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) VSS VCC Connecting Pattern Connecting Pattern Bypass Capacitor Figure 19.4 Bypass Capacitor Connection Rev. 2.00 Feb.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 19. Usage Notes 19.15 Instruction for a Device Use When handling a device, extra attention is necessary to prevent it from crashing during the electrostatic discharge period. Rev. 2.00 Feb.
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Appendix 1. Package Dimensions M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Appendix 1. Package Dimensions JEITA Package Code P-LQFP48-7x7-0.50 RENESAS Code PLQP0048KB-A Previous Code 48P6Q-A MASS[Typ.] 0.2g HD *1 D 36 25 NOTE) 1. DIMENSIONS "*1" AND "*2" 37 24 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Appendix 2. Functional Difference Appendix 2. Functional Difference Appendix 2.1 Differences between M16C/26A, M16C/26B, and M16C/26T Item Main Clock during and after Reset M16C/26A, M16C/26B Oscillating (Default value “0” while and after the CM05 bit is reset.
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Appendix 2. Functional Difference M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Appendix 2.
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Register Index M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Register Index A AD0 to AD7 184 ADCON0 to ADCON2 182 ADIC 67 ADSTAT0 184 ADTRGCON 183 AIER 79 IFSR2A 68 INT0IC to INT2IC INT3IC 67 INT4IC 67 INT5IC 67 INVC0 119 INVC1 120 67 K B KUPIC 67 BCNIC 67 N C NDDR CM0 40 CM1 41 227 O CM2 42 CPSRF 96, 110 CRCD 214 CRCIN 214 CRCMR 214 CRCSAR 214 ONSF 96 P P0 to P13 224 P17DDR 227 PACR 139, 226 PCLKR 43 PCR 226 PD0 to PD13 223 PDRF 129 PFCR 131 PLC0 44 PM0 35 PM1 35 PM2 36, 43 PRCR 60 PUR0 t
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Register Index M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) T W TA0 to TA4 95 TA0IC to TA4IC 67 TA0MR to TA4MR 94 TA1 122 TA11 122 TA1MR 125 TA2 122 TA21 122 TA2MR 125 TA2MR to TA4MR 101 TA4 122 TA41 122 TA4MR 125 TABSR 95, 110, 124 TAiMR 99, 106 TB0 to TB5 110 WDC 81 WDTS 81 TB0IC TO TB2IC 67 TB0MR to TB5MR 109 TB2 124 TB2MR 125 TB2SC 123, 185 TCR0 86 TCR1 86 TPRC 131 TRGSR 96, 124 U U0BRG to U2BRG 136 U0C0 to U2C0 138 U0C1 to U2C1 139 U0MR to U2MR 137 U0RB to U2RB 136 U0TB to U2TB 136 U2SMR 140 U2
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REVISION HISTORY M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Hardware Manual Rev. Date Description Summary Page 2.00 Feb.15,07 1 2-3 4-5 6 7 8 12, 14 15 - 16 20 22 23 28 29 35 36 37 41 43 45 - 46 47 50 51 54 55 56 59 60 76 M16C/26B newly added, word standardized: on-chip oscillator, development tool Overview •Description partially deleted •1.2 Performance Outline modified •Figure 1.1 and 1.2 Block Diagrams updated •1.4 Product List updated •Figure 1.3 Product Numbering System updated •Tables 1.
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REVISION HISTORY M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Hardware Manual Rev. Date Description Summary Page ______ 77 78 80 81 108 115 121 123 131 133 136 138 139 142 145 150 154 158 168 175 177 180 183 205 212 •9.7 NMI Interrupt Description partially added •Table 9.9.1 Value of the PC that is saved to the stack area when an address match interrupt request is accepted modified, note 1 added Watchdog Timer •Section of Cold Start/Warm Start deleted •Description partially added •Figure 10.
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REVISION HISTORY M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Hardware Manual Rev. Date Description Summary Page 1 added CRC Calculation Circuit 213 •15.1 CRC Snoop Description partially modified 214 •Figure 15.2 CRCSAR Register note 1 added Programable I/O Ports 216 •16.3 Pull-up Control Register 0 to Pull-up Control Register 2 description modified 217 •16.6 Digital Debounce function equation modified 218 - 221 •Figure 16.1 I/O Ports (1) to 16.4 I/O Ports (4) modified 227 •Figure 16.6.
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REVISION HISTORY M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Hardware Manual Rev. Date Description Summary Page 283 284 286 293 299 306 312 315 319 321 326 •Tables 18.41 and 18.42 Flash Memory Version Electrical Characteristics note 4 , note 10, note 11 modified •Figure for td(P-R) and td(ROC) modified •Table 18.45 Electrical Characteristics note 4 deleted •Table 18.60 Electrical Characteristics (2) note 4 deleted Usage Notes •19.1.3 Register Setting newly added •19.5.
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RENESAS 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER HARDWARE MANUAL M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Publication Date: Rev.1.00 Mar.15, 2005 Rev.2.00 Feb.15, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. © 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0202-0200