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To our customers,

Old Company Name in Catalogs and Other Documents

On April 1

, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corporation took over all the business of both

companies. Therefore, although the old company name remains in this document, it is a valid

Renesas Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1

, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry

Summary of content (412 pages)

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To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
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Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
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16 M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual RENESAS MCU M16C FAMILY / M16C/60 SERIES All information contained in this material, including products and product specifications at the time of publication of this material, is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website Rev.2.
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Keep safety first in your circuit designs! • Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1.
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How to Use This Manual 1. Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual.
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2. Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word “register,” “bit,” or “pin” to distinguish the three categories.
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3. Register Notation The symbols and terms used in register diagrams are described below. XXX Register b7 b6 b5 b4 b3 b2 b1 *1 b0 0 0 Symbol XXX Bit Symbol Address XXX After Reset 00h Bit Name Function RW b1 b0 XXX0 XXX bits XXX1 (b2) (b4-b3) 0 0: XXX 0 1: XXX 1 0: Do not set a value 1 1: XXX Reserved bits Set to 0 XXX bits Function varies depending on operating mode XXX6 *2 RW Nothing is assigned. If necessary, set to 0, When read, the content is undefined.
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4.
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Table of Contents SFR Page Reference ............................................................................................................ B-1 1. Overview ............................................................................................................................... 1 1.1 Applications .................................................................................................................................................. 1 1.2 Performance Overview .............................
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7.2 Bus Control ................................................................................................................................................ 46 7.2.1 Address Bus ....................................................................................................................................... 46 7.2.2 Data Bus ............................................................................................................................................ 46 7.2.3 Chip Select Signal .......
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10.5.4 Interrupt Sequence .......................................................................................................................... 89 10.5.5 Interrupt Response Time .................................................................................................................. 90 10.5.6 Variation of IPL when Interrupt Request is Accepted ....................................................................... 90 10.5.7 Saving Registers .....................................................
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16. A/D Converter .................................................................................................................. 202 16.1 Mode Description ................................................................................................................................... 206 16.1.1 One-shot Mode .............................................................................................................................. 206 16.1.2 Repeat Mode ..............................................
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21. Flash Memory Version .................................................................................................... 260 21.1 Memory Map .......................................................................................................................................... 261 21.1.1 Boot Mode ...................................................................................................................................... 262 21.2 Functions to Prevent Flash Memory from Rewriting .............
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23.11 Thee-Phase Motor Control Timer Function .......................................................................................... 356 23.12 Serial Interface ..................................................................................................................................... 357 23.12.1 Clock Synchronous Serial I/O Mode ............................................................................................ 357 23.12.2 Special Modes .................................................
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SFR Page Reference Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh Register Symbol Page Processor Mode Register 0 Processor Mode Register 1 System Clock Control Reg
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Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh Register Symbol Page Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00C
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Address 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h 011Ah 011Bh 011Ch 011Dh 011Eh 011Fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch 012Dh 012Eh 012Fh 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh Register Symbol Page Address 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014
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Address 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh Register Symbol Flash Memory Control Register 1 FMR1 266 Flash Memory Control Register 0 FMR0 266 Address Match
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Address 0200h 0201h 0202h 0203h 0204h 0205h 0206h 0207h 0208h 0209h 020Ah 020Bh 020Ch 020Dh 020Eh 020Fh 0210h 0211h 0212h 0213h 0214h 0215h 0216h 0217h 0218h 0219h 021Ah 021Bh 021Ch 021Dh 021Eh 021Fh 0220h 0221h 0222h 0223h 0224h 0225h 0226h 0227h 0228h 0229h 022Ah 022Bh 022Ch 022Dh 022Eh 022Fh 0230h 0231h 0232h 0233h 0234h 0235h 0236h 0237h 0238h 0239h 023Ah 023Bh 023Ch 023Dh 023Eh 023Fh Register CAN0 Message Control Register 0 CAN0 Message Control Register 1 CAN0 Message Control Register 2 CAN0 Message C
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Address 0280h 0281h 0282h 0283h 0284h 0285h 0286h 0287h 0288h 0289h 028Ah 028Bh 028Ch 028Dh 028Eh 028Fh 0290h 0291h 0292h 0293h 0294h 0295h 0296h 0297h 0298h 0299h 029Ah 029Bh 029Ch 029Dh 029Eh 029Fh 02A0h 02A1h 02A2h 02A3h 02A4h 02A5h 02A6h 02A7h 02A8h 02A9h 02AAh 02ABh 02ACh 02ADh 02AEh 02AFh 02B0h 02B1h 02B2h 02B3h 02B4h 02B5h 02B6h 02B7h 02B8h 02B9h 02BAh 02BBh 02BCh 02BDh 02BEh 02BFh Register Symbol Page Address 02C0h 02C1h 02C2h 02C3h 02C4h 02C5h 02C6h 02C7h 02C8h 02C9h 02CAh 02CBh 02CCh 02CDh 02C
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Address 0300h 0301h 0302h 0303h 0304h 0305h 0306h 0307h 0308h 0309h 030Ah 030Bh 030Ch 030Dh 030Eh 030Fh 0310h 0311h 0312h 0313h 0314h 0315h 0316h 0317h 0318h 0319h 031Ah 031Bh 031Ch 031Dh 031Eh 031Fh 0320h 0321h 0322h 0323h 0324h 0325h 0326h 0327h 0328h 0329h 032Ah 032Bh 032Ch 032Dh 032Eh 032Fh 0330h 0331h 0332h 0333h 0334h 0335h 0336h 0337h 0338h 0339h 033Ah 033Bh 033Ch 033Dh 033Eh 033Fh Register Symbol Page Address 0340h 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034Ah 034Bh 034Ch 034Dh 034
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Address 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038Ah 038Bh 038Ch 038Dh 038Eh 038Fh 0390h 0391h 0392h 0393h 0394h 0395h 0396h 0397h 0398h 0399h 039Ah 039Bh 039Ch 039Dh 039Eh 039Fh 03A0h 03A1h 03A2h 03A3h 03A4h 03A5h 03A6h 03A7h 03A8h 03A9h 03AAh 03ABh 03ACh 03ADh 03AEh 03AFh 03B0h 03B1h 03B2h 03B3h 03B4h 03B5h 03B6h 03B7h 03B8h 03B9h 03BAh 03BBh 03BCh 03BDh 03BEh 03BFh Register Count Start Flag Clock Prescaler Reset Flag One-Shot Start Flag Trigger Select Register Up/Down Flag Symbol T
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M16C/6N Group (M16C/6NK, M16C/6NM) Renesas MCU 1. Overview The M16C/6N Group (M16C/6NK, M16C/6NM) of MCUs are built using the high-performance silicon gate CMOS process using the M16C/60 Series CPU core and are packaged in 100-pin and 128-pin plastic molded LQFP. These MCUs operate using sophisticated instructions featuring a high level of instruction efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed.
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M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview 1.2 Performance Overview Tables 1.1 and 1.2 list the Functions and Specifications for M16C/6N Group (M16C/6NK, M16C/6NM). Table 1.1 Functions and Specifications for M16C/6N Group (100-pin Version: M16C/6NK) Specification Item Normal-ver. T/V-ver. CPU Number of fundamental 91 instructions instructions Minimum instruction 41.7 ns (f(BCLK) = 24 MHz, 50.
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M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Table 1.
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M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview 1.3 Block Diagram Figure 1.1 shows a Block Diagram. 8 Port P0 8 8 Port P1 Port P3 INTB PC Rev.2.10 Apr 14, 2006 REJ09B0124-0210 page 4 of 378 Port P13 (3) (3) 2 8 Port P12 (3) 8 Port P11 (3) 8 8 Figure 1.1 Block Diagram Multiplier FLG Port P14 NOTES: 1: ROM size depends on MCU type. 2: RAM size depends on MCU type. 3: Ports P11 to P14 are only in the 128-pin version. 4: 8 bits ✕ 2 channels in the 100-pin version.
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M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview 1.4 Product Information Table 1.3 lists the Product Information and Figure 1.2 shows the Type Number, Memory Size, and Packages. Table 1.3 Product Information Type No. M306NKFHGP M306NMFHGP M306NKFJGP M306NMFJGP M306NKFHTGP M306NMFHTGP M306NKFJTGP M306NMFJTGP M306NKFHVGP M306NMFHVGP M306NKFJVGP M306NMFJVGP M306NKME-XXXGP As of Apr.
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M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview 1.5 Pin Assignments 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P1_3/D11 P1_4/D12 P1_5/D13/INT3 P1_6/D14/INT4 P1_7/D15/INT5 P2_0/AN2_0/A0(/D0/-) P2_1/AN2_1/A1(/D1/D0) P2_2/AN2_2/A2(/D2/D1) P2_3/AN2_3/A3(/D3/D2) P2_4/AN2_4/A4(/D4/D3) P2_5/AN2_5/A5(/D5/D4) P2_6/AN2_6/A6(/D6/D5) P2_7/AN2_7/A7(/D7/D6) VSS P3_0/A8(/-/D7) VCC2 P3_1/A9 P3_2/A10 P3_3/A11 P3_4/A12 P3_5/A13 P3_6/A14 P3_7/A15 P4_0/A16 P4_1/A17 Figures 1.3 and 1.
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M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Table 1.4 List of Pin Names for 100-Pin Package (1) Pin No.
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M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Table 1.5 List of Pin Names for 100-Pin Package (2) Pin No.
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VREF AVCC P9_7/ADTRG/SIN4 P9_6/ANEX1/CTX0/SOUT4 P9_5/ANEX0/CRX0/CLK4 P9_4/DA1/TB4IN P9_3/DA0/TB3IN P9_2/TB2IN/SOUT3 (1) P9_1/TB1IN/SIN3 P9_0/TB0IN/CLK3 P14_1 P14_0 BYTE CNVSS P8_7/XCIN P8_6/XCOUT RESET XOUT VSS XIN VCC1 P8_5/NMI P8_4/INT2/ZP P8_3/INT1 P8_2/INT0 P8_1/TA4IN/U P8_0/TA4OUT/U(SIN4) P7_7/TA3IN/CRX1 P7_6/TA3OUT/CTX1 P7_5/TA2IN/W(SOUT4) P7_4/TA2OUT/W(CLK4) P7_3/CTS2/RTS2/TA1IN/V P7_2/CLK2/TA1OUT/V (1) P7_1/RXD2/SCL2/TA0IN/TB5IN P7_0/TXD2/SDA2/TA0OUT P6_7/TXD1/SDA1 VCC1 P6_6/RXD1/SCL1 Rev.2.
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M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Table 1.6 List of Pin Names for 128-Pin Package (1) Pin No.
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M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Table 1.7 List of Pin Names for 128-Pin Package (2) Pin No.
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M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Table 1.8 List of Pin Names for 128-Pin Package (3) Pin No.
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M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview 1.6 Pin Functions Tables 1.9 to 1.11 list the Pin Functions. Table 1.9 Pin Functions (100-pin and 128-pin Versions) (1) Signal Name Power supply input Analog power supply input Reset input CNVSS (2) Pin Name VCC1, VCC2, VSS AVCC, AVSS I/O Type Description I Apply 3.0 to 5.
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M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Table 1.10 Pin Functions (100-pin and 128-pin Versions) (2) Signal Name Main clock input Main clock output Sub clock input Sub clock output BCLK output (3) Clock output INT interrupt input _______ NMI interrupt input Key input interrupt input Timer A XIN Pin Name I XOUT O XCIN I XCOUT O BCLK CLKOUT NT0 to INT8 (2) ________ NMI O O I I Description I/O pins for the main clock oscillation circuit.
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M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Table 1.11 Pin Functions (100-pin and 128-pin Versions) (3) Signal Name I/O port Pin Name P0_0 to P0_7 I/O Type Description 8-bit I/O ports in CMOS, having a direction register to select I/O P1_0 to P1_7 an input or output. P2_0 to P2_7 Each pin is set as an input port or output port.
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M16C/6N Group (M16C/6NK, M16C/6NM) 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two register banks.
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M16C/6N Group (M16C/6NK, M16C/6NM) 2. Central Processing Unit (CPU) 2.3 Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 Program Counter (PC) PC is configured with 20 bits, indicating the address of an instruction to be executed. 2.
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M16C/6N Group (M16C/6NK, M16C/6NM) 3. Memory 3. Memory Figure 3.1 shows a Memory Map. The address space extends the 1 Mbyte from address 00000h to FFFFFh. The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 512-Kbyte internal ROM is allocated to the addresses from 80000h to FFFFFh. As for the flash memory version, 4-Kbyte space (block A) exists in 0F000h to 0FFFFh. 4-Kbyte space is mainly for storing data.
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M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) 4. Special Function Registers (SFRs) An SFR (Special Function Register) is a control register for a peripheral function. Tables 4.1 to 4.16 list the SFR Information. Table 4.
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M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.
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M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.
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M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.
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M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.
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M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.
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M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.
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M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.
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M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.
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M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.
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M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.
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M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.
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M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.
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M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.
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M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.
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M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Registers (SFRs) Table 4.
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M16C/6N Group (M16C/6NK, M16C/6NM) 5. Resets 5. Resets Hardware reset, software reset, watchdog timer reset, and oscillation stop detection reset are available to reset the MCU. 5.1 Hardware Reset ____________ The MCU resets pins, the CPU and SFR by setting the RESET pin. If the supply voltage ___________ meets the recommended operating conditions, the MCU resets all pins when an “L” signal is applied to the RESET pin ____________ (see Table 5.1 Pin Status When RESET Pin Level is “L”).
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M16C/6N Group (M16C/6NK, M16C/6NM) 5. Resets VCC XIN td(P-R) More than 20 cycles are needed RESET BCLK 28cycles BCLK Microprocessor mode BYTE = H (1) Content of reset vector FFFFCh Address FFFFDh FFFFEh RD WR CS0 Microprocessor mode BYTE = L (1) Content of reset vector FFFFCh Address FFFFEh RD WR CS0 Single-chip mode FFFFCh Content of reset vector FFFFEh Address NOTE: 1. Not available in T/V-ver. Figure 5.2 Reset Sequence ____________ Table 5.
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M16C/6N Group (M16C/6NK, M16C/6NM) 5. Resets 5.2 Software Reset The MCU resets pins, the CPU and SFR when the PM03 bit in the PM0 register is set to 1 (MCU reset). Then the MCU executes the program in an address determined by the reset vector. Set the PM03 bit to 1 while the main clock is selected as the CPU clock and the main clock oscillation is stable. In the software reset, the MCU does not reset a part of the SFR. Refer to 4. Special Function Registers (SFRs) for details.
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M16C/6N Group (M16C/6NK, M16C/6NM) 6. Processor Mode 6. Processor Mode Note 6. Processor Mode explains as an example of a Normal-ver.. T/V-ver. is available single-chip mode only. Not available memory expansion mode and microprocessor mode. 6.1 Types of Processor Mode Three processor modes are available to choose from: single-chip mode, memory expansion mode, and microprocessor mode. (Not available memory expansion and microprocessor modes in T/V-ver..) Table 6.1 shows the Features of Processor Modes.
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M16C/6N Group (M16C/6NK, M16C/6NM) 6. Processor Mode 6.2 Setting Processor Modes Processor mode is set by using the CNVSS pin and bits PM01 to PM00 in the PM0 register. Table 6.2 shows the Processor Mode after Hardware Reset. Table 6.3 shows the PM01 to PM00 bits set values and processor modes. Table 6.2 Processor Mode after Hardware Reset CNVSS Pin Input Level VSS VCC (1) (2) (3) Processor Mode Single-chip mode Microprocessor mode NOTES: 1.
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M16C/6N Group (M16C/6NK, M16C/6NM) 6.
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M16C/6N Group (M16C/6NK, M16C/6NM) 6.
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M16C/6N Group (M16C/6NK, M16C/6NM) 6.
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M16C/6N Group (M16C/6NK, M16C/6NM) 6.
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M16C/6N Group (M16C/6NK, M16C/6NM) 6.
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M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus 7. Bus Note 7. Bus explains as an example of a Normal-ver.. Not available the bus control pins in T/V-ver.. During memory expansion or microprocessor mode, some pins serve as the bus control pins to perform data _______ _______ input/output to and from external devices. These bus control pins include A0 to A19, D0 to D15, CS0 to CS3, _____ ________ ______ ________ ________ ________ __________ _________ RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and BCLK. 7.
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M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus 7.2 Bus Control The following describes the signals needed for accessing external devices and the functionality of software wait. Table 7.2 Bits PM06 and PM11 Set Value and Address Bus Width 7.2.1 Address Bus The address bus consists of 20 lines, A0 to A19. The address bus width can be chosen to be 12, 16 or 20 bits by using the PM06 bit in the PM0 register and the PM11 bit in the PM1 register. Table 7.2 shows Bits PM06 and PM11 Set Values and Address Bus Widths.
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M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus Example 1 Example 2 To access the external area indicated by CSj in the next cycle after accessing the external area indicated by CSi. To access the internal ROM or internal RAM in the next cycle after accessing the external area indicated by CSi. The address bus and the chip select signal both change state between these two cycles. The chip s elect s ignal c hanges state but the address bus does not change state.
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M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus 7.2.4 Read and Write Signals _____ When the________ data bus is 16-bit width, _____ the read and write signals can be chosen to be a combination of RD, ______ ________ ________ WR, and BHE or a combination of RD, WRL, and_____ WRH by using the PM02 bit in the PM0 register. When ______ ________ the data bus is 8-bit width, use a combination of RD, WR, and BHE. _____ ________ _________ _____ Table 7.3 shows the Operation of RD, WRL, and WRH Signals. Table 7.
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M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus ________ 7.2.6 RDY Signal This________ signal is provided for accessing external devices which need to be accessed at low speed. If input on the RDY pin is asserted low at the last falling edge of BCLK of the bus cycle, one wait state is inserted in ________ the bus cycle. While in a wait state, the following signals retain the state in which they were when the RDY signal was acknowledged.
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M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus __________ 7.2.7 HOLD Signal This signal is used to transfer control of the bus from the CPU or DMAC to an external circuit. When the __________ input on HOLD pin is pulled low, the MCU is placed__________ in a hold state after the bus access then in__________ process finishes. The MCU remains in a hold state while the HOLD pin is held low, during which time the HLDA pin outputs a low-level signal. Table 7.5 shows the MCU Status in Hold State.
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M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus Table 7.
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M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus 7.2.9 External Bus Status when Internal Area Accessed Table 7.7 shows the External Bus Status When Internal Area Accessed. Table 7.
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M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus Table 7.
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M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus (1) Separate bus, No wait setting Bus cycle (1) Bus cycle (1) BCLK Write signal Read signal Data bus Address bus Output Address Input Address CS (2) Separate bus, 1-wait setting Bus cycle (1) Bus cycle (1) BCLK Write signal Read signal Data bus Address bus Output Input Address Address CS (3) Separate bus, 2-wait setting Bus cycle (1) Bus cycle (1) BCLK Write signal Read signal Data bus Address bus Output Address Input Address CS NOTE: 1.
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M16C/6N Group (M16C/6NK, M16C/6NM) 7.
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M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generation Circuit 8. Clock Generation Circuit 8.1 Types of Clock Generation Circuit Four circuits are incorporated to generate the system clock signal: • Main clock oscillation circuit • Sub clock oscillation circuit • On-chip oscillator • PLL frequency synthesizer Table 8.1 lists the Clock Generation Circuit Specifications. Figure 8.1 shows the Clock Generation Circuit. Figures 8.2 to 8.8 show the clock-related registers. Table 8.
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M16C/6N Group (M16C/6NK, M16C/6NM) 8.
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M16C/6N Group (M16C/6NK, M16C/6NM) 8.
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M16C/6N Group (M16C/6NK, M16C/6NM) 8.
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M16C/6N Group (M16C/6NK, M16C/6NM) 8.
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M16C/6N Group (M16C/6NK, M16C/6NM) 8.
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M16C/6N Group (M16C/6NK, M16C/6NM) 8.
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M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generation Circuit PLL Control Register 0 (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset PLC0 001Ch 0001X010b Bit Symbol Bit Name 0 0 1 Function RW b2 b1 b0 PLC00 PLC01 PLL multiplying factor select bits (2) PLC02 (b3) - 0 0 0 : Do not set a value 0 0 1 : Multiply-by-2 0 1 0 : Multiply-by-4 0 1 1 : Multiply-by-6 (4) 100: 101: Do not set a value 110: 111: Nothing is assigned. If necessary, set to 0.
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M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generation Circuit The following describes the clocks generated by the clock generation circuit. 8.1.1 Main Clock The main clock is generated by the main clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks. The main clock oscillation circuit is configured by connecting a resonator between pins XIN and XOUT.
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M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generation Circuit 8.1.2 Sub Clock The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for the CPU clock, as well as the timer A and timer B count sources. In addition, an fC clock with the same frequency as that of the sub clock can be output from the CLKOUT pin. The sub clock oscillation circuit is configured by connecting a crystal resonator between pins XCIN and XCOUT.
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M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generation Circuit 8.1.3 On-chip Oscillator Clock This clock, approximately 1 MHz, is supplied by a on-chip oscillator. This clock is used as the clock source for the CPU and peripheral function clocks. In addition, if the PM22 bit in the PM2 register is 1 (on-chip oscillator clock for the watchdog timer count source), this clock is used as the count source for the watchdog timer (refer to 11.1 Count Source Protective Mode).
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M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generation Circuit Using the PLL clock as the clock source for the CPU Set the CM07 bit to 0 (main clock), bits CM17 to CM16 to 00b (main clock undivided), and the CM06 bit to 0 (bits CM16 and CM17 enabled). (1) Set bits PLC02 to PLC00 (multiplying factor). (When PLL clock > 16 MHz) Set the PM20 bit to 0 (2-wait state). Set the PLC07 bit to 1 (PLL operation). Wait until the PLL clock becomes stable (tsu(PLL)).
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M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generation Circuit 8.2 CPU Clock and Peripheral Function Clock Two type clocks: CPU clock to operate the CPU and peripheral function clocks to operate the peripheral functions. 8.2.1 CPU Clock and BCLK These are operating clocks for the CPU and watchdog timer. The clock source for the CPU clock can be chosen to be the main clock, sub clock, on-chip oscillator clock or the PLL clock.
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M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generation Circuit 8.4 Power Control Normal operating mode, wait mode and stop mode are provided as the power consumption control. All mode states, except wait mode and stop mode, are called normal operating mode in this document. 8.4.1 Normal Operating Mode Normal operating mode is further classified into seven sub modes.
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M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generation Circuit 8.4.1.6 On-chip Oscillator Mode The on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The on-chip oscillator clock is also the clock source for the peripheral function clocks. If the sub clock is on, fC32 can be used as the count source for timers A and B. When the operating mode is returned to the high-speed and medium-speed modes, set the CM06 bit in the CM0 register to 1 (divide-by-8 mode). 8.4.1.
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M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generation Circuit 8.4.2 Wait Mode In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the watchdog timer. However, if the PM22 bit in the PM2 register is 1 (on-chip oscillator clock for the watchdog timer count source), the watchdog timer remains active. Because the main clock, sub clock and on-chip oscillator clock all are on, the peripheral functions using these clocks keep operating. 8.4.2.
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M16C/6N Group (M16C/6NK, M16C/6NM) Table 8.5 Interrupts to Exit Wait Mode and Use Conditions Interrupt CM02 Bit = 0 _______ NMI interrupt Can be used Serial interface interrupt Can be used when operating with internal or external clock Key input interrupt Can be used A/D conversion interrupt Can be used in one-shot mode or single sweep mode Timer A interrupt Can be used in all modes Timer B interrupt ______ INT interrupt Can be used CAN0/1 wake-up interrupt Can be used in CAN sleep mode 8.
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M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generation Circuit 8.4.3 Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least amount of power is consumed in this mode. If the voltage applied to VCC pin is VRAM or more, the internal RAM is retained. However, the peripheral functions clocked by external signals keep operating. Table 8.
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M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generation Circuit 8.4.3.3 Exiting Stop Mode _______ Stop mode is exited by a hardware reset, NMI interrupt or peripheral function interrupt. _______ When the hardware reset or NMI interrupt is used to exit stop mode, set all ILVL2 to ILVL0 bits in the interrupt control registers for the peripheral function interrupt to 000b (interrupt disabled) before setting the CM10 bit in the CM1 register to 1.
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M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generation Circuit Figure 8.12 shows the State Transition to Stop Mode and Wait Mode. Figure 8.13 shows the State Transition in Normal Operating Mode. Table 8.8 shows a state transition matrix describing allowed transition and setting. The vertical line shows current state and horizontal line show state after transition.
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M16C/6N Group (M16C/6NK, M16C/6NM) 8.
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M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generation Circuit Table 8.
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M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generation Circuit 8.5 Oscillation Stop and Re-oscillation Detection Function The oscillation stop and re-oscillation detection function is such that main clock oscillation circuit stop and re-oscillation are detected. At oscillation stop, re-oscillation detection, reset or oscillation stop, re-oscillation detection interrupt request are generated. Which is to be generated can be selected using the CM27 bit in the CM2 register.
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M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generation Circuit 8.5.3 How to Use Oscillation Stop and Re-oscillation Detection Function • The oscillation stop, re-oscillation detection interrupt shares the vector with the watchdog timer interrupt. If the oscillation stop, re-oscillation detection and watchdog timer interrupts both are used, read the CM22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt.
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M16C/6N Group (M16C/6NK, M16C/6NM) 9. Protection 9. Protection In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Figure 9.1 shows the PRCR Register. The registers protected by the PRCR register are listed below.
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M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupts 10. Interrupts 10.1 Type of Interrupts Figure 10.1 shows the Types of Interrupts.
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M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupts 10.2 Software Interrupts A software interrupt is generated when executing certain instructions. Software interrupts are nonmaskable interrupts. 10.2.1 Undefined Instruction Interrupt An undefined instruction interrupt is generated when executing the UND instruction. 10.2.2 Overflow Interrupt An overflow interrupt is generated when executing the INTO instruction with the O flag in the FLG register set to 1 (the operation resulted in an overflow).
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M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupts 10.3 Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts. 10.3.1 Special Interrupts Special interrupts are non-maskable interrupts. _______ 10.3.1.1 NMI Interrupt _______ _______ An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details, _______ refer to 10.7 NMI Interrupt. ________ 10.3.1.
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M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupts 10.4 Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt vector. Figure 10.2 shows the Interrupt Vector. MSB Vector address (L) LSB Low-order address Middle-order address Vector address (H) 0000 High-order address 0000 0000 Figure 10.
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M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupts Table 10.
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M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupts 10.5 Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to non-maskable interrupts. Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in the each interrupt control register to enable/disable the maskable interrupts.
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M16C/6N Group (M16C/6NK, M16C/6NM) 10.
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M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupts 10.5.1 I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to 1 (enabled) enables the maskable interrupt. Setting the I flag to 0 (disabled) disables all maskable interrupts. 10.5.2 IR Bit The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. Then, when the interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is set to 0 (interrupt not requested).
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M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupts 10.5.4 Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here. If an interrupt request is generated while an instruction is being executing, the CPU determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle.
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M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupts 10.5.5 Interrupt Response Time Figure 10.6 shows the Interrupt Response Time. The interrupt response or interrupt acknowledge time denotes a time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed. Specifically, it consists of a time from when an interrupt request is generated till when the instruction then executing is completed ((a) on Figure 10.
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M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupts 10.5.7 Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure 10.7 shows the Stack Status Before and After Acceptance of Interrupt Request.
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M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupts 10.5.8 Returning from Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine. Thereafter the CPU returns to the program which was being executed before accepting the interrupt request.
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M16C/6N Group (M16C/6NK, M16C/6NM) Priority level of each interrupt Level 0 (initial value) 10.
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M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupts ______ 10.6 INT Interrupt _______ INTi interrupt (i = 0 to 8) (1) is triggered by the edges of external inputs. The edge polarity is selected using bits IFSR10 to IFSR15 in the IFSR1 register and bits IFSR23 to IFSR25 in the IFSR2 register.
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M16C/6N Group (M16C/6NK, M16C/6NM) 10.
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M16C/6N Group (M16C/6NK, M16C/6NM) 10.
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M16C/6N Group (M16C/6NK, M16C/6NM) 10.
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M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupts ______ 10.7_______ NMI Interrupt _______ ______ An NMI interrupt request is generated when input on the NMI pin changes state from high to low. The NMI interrupt is a non-maskable interrupt. _______ The input level of this NMI interrupt input pin can be read by accessing the P8_5 bit in the P8 register. This pin cannot be used as an input port. 10.
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M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupts 10.10 Address Match Interrupt An address match interrupt request is generated immediately before executing the instruction at the address indicated by the RMADi register (i = 0 to 3). Set the start address of any instruction in the RMADi register. Use bits AIER0 and AIER1 in the AIER register and bits AIER20 and AIER21 in the AIER2 register to enable or disable the interrupt. Note that the address match interrupt is unaffected by the I flag and IPL.
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M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupts Address Match Interrupt Enable Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol AIER Address 0009h After Reset XXXXXX00b Bit Symbol Bit Name AIER0 AIER1 - Function RW Address match interrupt 0 enable bit 0 : Interrupt disabled 1 : Interrupt enabled RW Address match interrupt 1 enable bit 0 : Interrupt disabled 1 : Interrupt enabled RW Nothing is assigned. If necessary, set to 0. When read, the content is undefined.
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M16C/6N Group (M16C/6NK, M16C/6NM) 11. Watchdog Timer 11. Watchdog Timer The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter which counts down the clock derived by dividing the CPU clock using the prescaler.
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M16C/6N Group (M16C/6NK, M16C/6NM) 11.
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M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC 12. DMAC The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention. Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8- or 16-bit) data from the source address to the destination address. The DMAC uses the same data bus as used by the CPU.
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M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC Table 12.1 DMAC Specifications Item Specification No. of channels 2 (cycle steal method) Transfer memory space • From given address in the 1-Mbyte space to a fixed address • From a fixed address to given address in the 1-Mbyte space • From a fixed address to a fixed address Maximum no.
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M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC DMA0 Request Source Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DM0SL Address 03B8h Bit Symbol After Reset 00h Function Bit Name DSEL0 DSEL1 DSEL2 RW DMA request source select bits See NOTE 1 - DMS DSR RW RW RW DSEL3 (b5-b4) RW Nothing is assigned. If necessary, set to 0. When read, the content is 0.
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M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC DMA1 Request Source Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DM1SL Address 03BAh Bit Symbol After Reset 00h Function Bit Name RW DSEL0 DSEL1 DSEL2 RW DMA request source select bits RW See NOTE 1 RW RW DSEL3 (b5-b4) Nothing is assigned. If necessary, set to 0. When read, the content is 0.
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M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC DMAi Source Pointer (i = 0, 1) (1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol SAR0 SAR1 Address 0022h to 0020h 0032h to 0030h Function After Reset Undefined Undefined Setting Range Set the source address of transfer 00000h to FFFFFh Nothing is assigned. If necessary, set to 0. When read, the content is 0. RW RW - NOTE: 1.
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M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC 12.1 Transfer Cycle The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus cycle. The number of read and write bus cycles is affected by the source and destination addresses of transfer. During memory expansion and microprocessor modes, it is________ also affected by the BYTE pin level (1). Furthermore, the bus cycle itself is extended by a software wait or RDY signal (2). NOTES: 1.
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M16C/6N Group (M16C/6NK, M16C/6NM) 12.
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M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC 12.2 DMA Transfer Cycles Any combination of even or odd transfer read and write addresses is possible. Table 12.2 lists the DMA Transfer Cycles. Table 12.3 lists the Coefficient j, k. The number of DMAC transfer cycles can be calculated as follows: No. of transfer cycles per transfer unit = No. of read cycles ✕ j + No. of write cycles ✕ k Table 12.
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M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC 12.3 DMA Enable When a data transfer starts after setting the DMAE bit in the DMiCON register (i = 0, 1) to 1 (enabled), the DMAC operates as follows: (1) Reload the forward address pointer with the SARi register value when the DSD bit in the DMiCON register is 1 (forward) or the DARi register value when the DAD bit in the DMiCON register is 1 (forward). (2) Reload the DMAi transfer counter with the DMAi transfer counter reload register value.
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M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC 12.5 Channel Priority and DMA Transfer Timing If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are detected active in the same sampling period (one period from a falling edge to the next falling edge of BCLK), the DMAS bit on each channel is set to 1 (DMA requested) at the same time. In this case, the DMA requests are arbitrated according to the channel priority, DMA0 > DMA1.
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M16C/6N Group (M16C/6NK, M16C/6NM) 13. Timers 13. Timers Eleven 16-bit timers, each capable of operating independently of the others, can be classified by function as either timer A (five) and timer B (six). The count source for each timer acts as a clock, to control such timer operations as counting, reloading, etc. Figures 13.1 and 13.2 show the Timer A and Timer B Configurations.
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M16C/6N Group (M16C/6NK, M16C/6NM) 1/2 Main clock f1 PLL clock On-chip oscillator clock 13.
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M16C/6N Group (M16C/6NK, M16C/6NM) 13. Timers 13.1 Timer A Figure 13.3 shows the Timer A Block Diagram. Figures 13.4 to 13.6 show the timer A-related registers. The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the same function. Use bits TMOD1 to TMOD0 in the TAiMR register (i = 0 to 4) to select the desired mode. • Timer mode: The timer counts an internal count source.
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M16C/6N Group (M16C/6NK, M16C/6NM) 13.
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M16C/6N Group (M16C/6NK, M16C/6NM) 13.
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M16C/6N Group (M16C/6NK, M16C/6NM) 13.
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M16C/6N Group (M16C/6NK, M16C/6NM) 13. Timers 13.1.1 Timer Mode In timer mode, the timer counts a count source generated internally. Table 13.1 lists the Timer Mode Specifications. Figure 13.7 shows Registers TA0MR to TA4MR in Timer Mode. Table 13.
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M16C/6N Group (M16C/6NK, M16C/6NM) 13. Timers 13.1.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Timers A2, A3, and A4 can count two-phase external signals. Table 13.2 lists the Event Counter Mode Specifications (when not using two-phase pulse signal processing). Figure 13.8 shows TAiMR Register in Event Counter Mode (when not using two-phase pulse signal processing). Table 13.
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M16C/6N Group (M16C/6NK, M16C/6NM) 13.
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M16C/6N Group (M16C/6NK, M16C/6NM) 13. Timers Table 13.3 Event Counter Mode Specifications (when using two-phase pulse signal processing with timers A2, A3, and A4) Item Specification Count source • Two-phase pulse signals input to TAiIN or TAiOUT pins Count operation • Up-count or down-count can be selected by two-phase pulse signal • When the timer overflows or underflows, it reloads the reload register contents and continues counting.
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M16C/6N Group (M16C/6NK, M16C/6NM) 13. Timers Timer Ai Mode Register (i = 2 to 4) (When using two-phase pulse signal processing) b6 b5 b4 b3 b2 b1 b0 0 1 0 0 0 1 Symbol TA2MR to TA4MR Bit Symbol TMOD0 TMOD1 Address 0398h to 039Ah Bit Name After Reset 00h Function RW Operating mode select bits 0 1 : Event counter mode RW RW b1 b0 RW MR0 To use two-phase pulse signal processing, set this bit to 0. MR1 RW MR2 To use two-phase pulse signal processing, set this bit to 1.
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M16C/6N Group (M16C/6NK, M16C/6NM) 13. Timers 13.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing This function initializes the timer count value to 0 by Z-phase (counter initialization) input during twophase pulse signal processing. This function can only be used in timer A3 event counter mode during two-phase pulse signal processing, free-running type, x4 processing, with Z-phase entered from the ZP pin.
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M16C/6N Group (M16C/6NK, M16C/6NM) 13. Timers 13.1.3 One-shot Timer Mode In one-shot timer mode, the timer is activated only once by one trigger. When the trigger occurs, the timer starts up and continues operating for a given period. Table 13.4 lists the One-shot Timer Mode Specifications. Figure 13.11 shows Registers TA0MR to TA4MR in One-shot Timer Mode. Table 13.
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M16C/6N Group (M16C/6NK, M16C/6NM) 13.
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M16C/6N Group (M16C/6NK, M16C/6NM) 13. Timers 13.1.4 Pulse Width Modulation (PWM) Mode In Pulse Width Modulation mode, the timer outputs pulses of a given width in succession. The counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Table 13.5 lists the Pulse Width Modulation Mode Specifications. Figure 13.12 shows Registers TA0MR to TA4MR in Pulse Width Modulation Mode. Figures 13.13 and 13.
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M16C/6N Group (M16C/6NK, M16C/6NM) 13.
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M16C/6N Group (M16C/6NK, M16C/6NM) 13. Timers 16 1 / fi ✕ (2 – 1) Count source Input signal to TAiIN pin "H" PWM pulse output from TAiOUT pin "H" "L" Trigger is not generated by this signal 1 / fj ✕ n "L" IR bit in TAiIC register 1 0 Set to 0 upon accepting an interrupt request or by writing in program i = 0 to 4 fj: Frequency of count source (f1, f2, f8, f32, fC32) NOTES: 1. n = 0000h to FFFEh. 2. This timing diagram is the following case.
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M16C/6N Group (M16C/6NK, M16C/6NM) 13. Timers 13.2 Timer B Figure 13.15 shows a Timer B Block Diagram. Figures 13.16 and 13.17 show the timer B-related registers. Timer B supports the following three modes. Use bits TMOD1 and TMOD0 in the TBiMR register (i = 0 to 5) to select the desired mode. • Timer mode : The timer counts an internal count source. • Event counter mode : The timer counts pulses from an external device or over flows or underflows of other timers.
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M16C/6N Group (M16C/6NK, M16C/6NM) 13.
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M16C/6N Group (M16C/6NK, M16C/6NM) 13.
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M16C/6N Group (M16C/6NK, M16C/6NM) 13. Timers 13.2.1 Timer Mode In timer mode, the timer counts a count source generated internally. Table 13.6 lists the Timer Mode Specifications. Figure 13.18 shows Registers TB0MR to TB5MR in Timer Mode. Table 13.
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M16C/6N Group (M16C/6NK, M16C/6NM) 13. Timers 13.2.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Table 13.7 lists the Event Counter Mode Specifications. Figure 13.19 shows Registers TB0MR to TB5MR in Event Counter Mode. Table 13.
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M16C/6N Group (M16C/6NK, M16C/6NM) 13. Timers 13.2.3 Pulse Period and Pulse Width Measurement Mode In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an external signal. Table 13.8 lists the Pulse Period and Pulse Width Measurement Mode Specifications. Figure 13.20 shows Registers TB0MR to TB5MR in Pulse Period and Pulse Width Measurement mode. Figure 13.21 shows the Operation Timing when Measuring Pulse Period. Figure 13.
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M16C/6N Group (M16C/6NK, M16C/6NM) 13.
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M16C/6N Group (M16C/6NK, M16C/6NM) 13.
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M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control Timer Function 14. Three-Phase Motor Control Timer Function Timers A1, A2, A4, and B2 can be used to output three-phase motor drive waveforms. Table 14.1 lists the Three-phase Motor Control Timer Function Specifications. Figure 14.1 shows the Three-phase Motor Control Timer Function Block Diagram. Figures 14.2 to 14.8 shows the Three-phase Motor Control Timer Function related registers. Table 14.
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M16C/6N Group (M16C/6NK, M16C/6NM) 14.
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M16C/6N Group (M16C/6NK, M16C/6NM) 14.
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M16C/6N Group (M16C/6NK, M16C/6NM) 14.
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M16C/6N Group (M16C/6NK, M16C/6NM) 14.
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M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control Timer Function Timer Ai, Ai-1 Register (i = 1, 2, 4) (1) (2) (3) (4) (5) (6) b15 b8 b7 b0 Symbol TA1, TA2, TA4 TA11, TA21, TA41 (7) Address 0389h - 0388h, 038Bh - 038Ah, 038Fh - 038Eh 01C3h - 01C2h, 01C5h - 01C4h, 01C7h - 01C6h Function If setting value is n, the timer stops when the nth count source is counted after a start trigger is generated. Positive phase changes to negative phase, and vice versa, when timers A1, A2, and A4 stop.
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M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control Timer Function Timer B2 Interrupt Generation Frequency Set Counter (1) (2) (3) b7 b0 Symbol ICTB2 Address 01CDh After Reset Undefined Function Setting Range RW When the INV01 bit in the INVC0 register is set to 0 (the ICTB2 counter increments whenever the timer B2 underflows) and the setting value is n, the timer B2 interrupt is generated every nth time timer B2 underflow occurs.
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M16C/6N Group (M16C/6NK, M16C/6NM) 14.
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M16C/6N Group (M16C/6NK, M16C/6NM) 14.
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M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control Timer Function The three-phase motor control timer function is enabled by setting the INV02 bit in the INVC0 register to 1. When this function is selected, timer B2 is used to__control the carrier wave, and timers A4, A1, and A2 are ___ ___ used to control three-phase PWM outputs (U, U, V, V, W, and W). The dead time is controlled by a dedicated dead-time timer. Figure 14.
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M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control Timer Function Sawtooth waveform as a carrier wave Sawtooth wave Signal wave Timer B2 Timer A4 start trigger signal(1) Timer A4 one-shot pulse(1) Rewrite registers IDB0 and IDB1 Transfer the counter to the three-phase shift register U-Phase output (1) signal U-Phase output signal(1) U-phase INV14 = 0 ("L" active) Dead time U-phase U-phase INV14 = 1 ("H" active) Dead time U-phase INV14: Bits in the INVC1 register NOTES: 1.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface 15. Serial Interface Serial interface is configured with 7 channels: UART0 to UART2 and SI/O3 to SI/O6 (1). NOTE: 1. 100-pin version supports 5 channels; UART0 to UART2, SI/O3, SI/O4 128-pin version supports 7 channels; UART0 to UART2, SI/O3 to SI/O6 15.1 UARTi (i = 0 to 2) UARTi each have an exclusive timer to generate a transfer clock, so they operate independently of each other. Figures 15.1 to 15.3 show the UARTi Block Diagram. Figure 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface UARTi Transmit Buffer Register (i = 0 to 2) (1) (b15) b7 (b8) b0 b7 b0 Symbol Address U0TB U1TB U2TB 03A3h to 03A2h 03ABh to 03AAh 01FBh to 01FAh Bit Symbol (b8-b0) (b15-b9) After Reset Undefined Undefined Undefined RW Function Transmit data WO Nothing is assigned. If necessary, set to 0. When read, the content is undefined. - NOTE: 1. Use the MOV instruction to write to this register.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface UARTi Special Mode Register 2 (i = 0 to 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0SMR2 to U2SMR2 Address 01EEh, 01F2h, 01F6h Symbol Bit Bit Name IICM2 I2C mode select bit 2 CSC Clock-synchronous bit SWC ALS STAC SWC2 SDHI (b7) After Reset X0000000b RW Function See Table 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface UARTi Special Mode Register 4 (i = 0 to 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0SMR4 to U2SMR4 Bit Symbol Bit Name Start condition generate bit (1) Restart condition RSTAREQ generate bit (1) Stop condition STPREQ generate bit (1) SCL,SDA output STSPSEL select bit STAREQ ACKD ACKC SCLHI SWC9 ACK data bit ACK data output enable bit SCL output stop enable bit SCL wait bit 3 NOTE: 1. Set to 0 when each condition is generated. Figure 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface 15.1.1 Clock Synchronous Serial I/O Mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 15.1 lists the Clock Synchronous Serial I/O Mode Specifications. Table 15.2 lists the Registers to be Used in and Setting in Clock Synchronous Serial I/O Mode. Table 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Table 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Table 15.3 lists the I/O Pin Functions (when not select multiple transfer clock output pin select function) in clock synchronous serial I/O mode. Table 15.4 lists the P6_4 Pin Functions in clock synchronous serial I/O mode. Note that for a period from when the UARTi operating mode is selected to when transfer starts, the TXDi pin outputs an “H”. Figure 15.11 shows the Transmit/Receive Operation during clock synchronous serial I/O mode. Table 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface 15.1.1.1 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode, follow the procedures below.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface 15.1.1.3 LSB First/MSB First Select Function Use the UFORM bit in the UiC0 register (i = 0 to 2) to select the transfer format. Figure 15.13 shows the Transfer Format.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface 15.1.1.5 Serial Data Logic Switching Function When the UiLCH bit in the UiC1 register (i = 0 to 2) = 1 (reverse), the data written to the UiTB register has its logic reversed before being transmitted. Similarly, the receive data has its logic reversed when read from the UiRB register. Figure 15.14 shows the Serial Data Logic Switching.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface _______ _______ 15.1.1.7 CTS/RTS Function _______ ________ ________ When the CTS function is used transmit and receive operation start when “L” is applied to the CTSi/RTSi ________ ________ (i = 0 to 2) pin. Transmit and receive operation begins when the CTSi/RTSi pin is held “L”. If the “L” signal is switched_______ to “H” during a transmit or ________ receive operation, the operation stops before the next data.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface 15.1.2 Clock Asynchronous Serial I/O (UART) Mode The UART mode allows transmitting and receiving data after setting the desired bit rate and transfer data format. Table 15.5 lists the UART Mode Specifications. Table 15.6 lists the Registers to be Used and Setting in UART Mode. Table 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Table 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Table 15.7 lists the I/O Pins Functions in UART mode. Table 15.8 lists the P6_4 Pin Functions in UART mode. Note that for a period from when the UARTi operating mode is selected to when transfer starts, the TXDi pin outputs an “H”. Figure 15.17 shows the Transmit Operation in UART mode. Figure 15.18 shows the Receive Operation in UART mode. Table 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface (1) 8-bit data transmit timing (with a parity and 1 stop bit) The transfer clock stops momentarily, because an "H" signal is applied to the CTS pin, when the stop bit is verified. The transfer clock resumes running as soon as an "L" signal is applied to the CTS pin.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface 15.1.2.2 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in UART mode, follow the procedures below.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface 15.1.2.4 Serial Data Logic Switching Function The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the UiRB register. Figure 15.20 shows the Serial Data Logic Switching.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface _______ _______ 15.1.2.6 CTS/RTS Function _______ ________ ________ When the CTS function is used transmit operation start when “L” is applied to the CTSi/RTSi (i = 0 to 2) ________ ________ pin. Transmit operation begins when the CTSi/RTSi pin is held “L”. If the “L” signal is switched to “H” during a transmit operation, the operation stops before the next data.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface 15.1.3 Special Mode 1 (I2C Mode) I2C mode is provided for use as a simplified I2C interface compatible mode. Table 15.10 lists the I2C Mode Specifications. Figure 15.23 shows the I2C Mode Block Diagram. Table 15.11 lists the Registers to be Used and Setting in I2C Mode. Table 15.12 lists the I2C Mode Functions. Figure 15.24 shows the Transfer to UiRB Register and Interrupt Timing. As shown in Table 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Table 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Table 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface 15.1.3.1 Detection of Start and Stop Condition Whether a start or a stop condition has been detected is determined. A start condition-detected interrupt request is generated when the SDAi pin changes state from high to low while the SCLi pin is in the high state. A stop condition-detected interrupt request is generated when the SDAi pin changes state from low to high while the SCLi pin is in the high state. Figure 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Table 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface 15.1.3.4 Transfer Clock Data is transmitted/received using a transfer clock like the one shown in Figure 15.24 Transfer to UiRB Register and Interrupt Timing. The CSC bit in the UiSMR2 register is used to synchronize the internally generated clock (internal SCLi) and an external clock supplied to the SCLi pin.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface 15.1.3.7 ACK and NACK If the STSPSEL bit in the UiSMR4 register is set to 0 (start and stop conditions not generated) and the ACKC bit in the UiSMR4 register is set to 1 (ACK data output), the value of the ACKD bit in the UiSMR4 register is output from the SDAi pin. If the IICM2 bit = 0, a NACK interrupt request is generated if the SDAi pin remains high at the rising edge of the 9th bit of transmit clock pulse.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface 15.1.4 Special Mode 2 Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are selectable. Table 15.14 lists the Special Mode 2 Specifications. Figure 15.27 shows the Serial Bus Communication Control Example (UART2). Table 15.15 lists the Registers to be Used an Settings in Special Mode 2. Table 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface P1_3 P1_2 P7_2(CLK2) P7_1(RXD2) P7_0(TXD2) MCU (Master) P9_3 P7_2(CLK2) P7_1(RXD2) P7_0(TXD2) MCU (Slave) P9_3 P7_2(CLK2) P7_1(RXD2) P7_0(TXD2) MCU (Slave) Figure 15.27 Serial Bus Communication Control Example (UART2) Rev.2.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Table 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface 15.1.4.1 Clock Phase Setting Function One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit in the UiSMR3 register and the CKPOL bit in the UiC0 register. Make sure the transfer clock polarity and phase are the same for the master and salves to be communicated. Figure 15.28 shows the Transmission and Reception Timing in Master Mode (internal clock). Figure 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface "H" Slave control input "L" Clock input "H" (CKPOL= 0, CKPH = 0) "L" Clock input "H" (CKPOL = 1, CKPH = 0) "L" Data output timing "H" D0 "L" Data input timing D1 D2 D3 D4 D5 D6 D7 Undefined Figure 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface 15.1.5 Special Mode 3 (IE Mode) In this mode, one bit of IEBus is approximated with one byte of UART mode waveform. Table 15.16 lists the Registers to be Used and Settings in IE mode. Figure 15.31 shows the Bus Collision Detect Function-Related Bits. If the TXDi pin (i = 0 to 2) output level and RXDi pin input level do not match, a UARTi bus collision detect interrupt request is generated.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface (1) The ABSCS bit in UiSMR register (bus collision detect sampling clock select) If ABSCS bit = 0, bus collision is determined at the rising edge of the transfer clock Transfer clock ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP TXDi RXDi Trigger signal is applied to the TAjIN pin Timer Aj If ABSCS bit = 1, bus collision is determined when timer Aj (one-shot timer mode) underflows.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface 15.1.6 Special Mode 4 (SIM Mode) (UART2) Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be implemented, and this mode allows to output a low from the TXD2 pin when a parity error is detected. Table 15.17 lists the SIM Mode Specifications. Table 15.18 lists the Registers to be Used and Settings in SIM Mode. Figure 15.32 shows the Transmit and Receive Riming in SIM Mode. Table 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Table 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) (1) Transmit timing 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Figure 15.33 shows the SIM Interface Connection. Connect TXD2 and RXD2 and apply pull-up. MCU SIM card TXD2 RXD2 Figure 15.33 SIM Interface Connection 15.1.6.1 Parity Error Signal Output The parity error signal is enabled by setting the U2ERE bit in the U2C1 register to 1 (output enabled). The parity error signal is output when a parity error is detected while receiving data.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface 15.1.6.2 Format When direct format, set the PRYE bit in the U2MR register to 1, the PRY bit to 1, the UFORM bit in the U2C0 register to 0 and the U2LCH bit in the U2C1 register to 0. When data are transmitted, data set in the U2TB register are transmitted with the even-numbered parity, starting from D0. When data are received, received data are stored in the U2RB register, starting from D0.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface 15.2 SI/Oi (i = 3 to 6) (1) SI/Oi is exclusive clock-synchronous serial I/Os. Figure 15.36 shows the SI/Oi Block Diagram, and Figures 15.37 and 15.38 show the SI/Oi-related registers. Table 15.19 lists the SI/Oi Specifications. NOTE: 1. 100-pin version supports SI/O3 and SI/O4. 128-pin version supports SI/O3, SI/O4, SI/O5 and SI/O6.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Table 15.19 SI/Oi Specifications Item Specification Transfer data format Transfer data length: 8 bits Transfer clock • SMi6 bit in SiC register = 1 (internal clock) : fj/(2(n+1)) Transmit/receive fj = f1SIO, f8SIO, f32SIO.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface 15.2.1 SI/Oi Operation Timing Figure 15.39 shows the SI/Oi Operation Timing. 0.5 to 1.0 cycle (max.) SI/Oi internal clock "H" "L" CLKi output "H" "L" Signal written to the SiTRR register "H" "L" SOUTi output "H" "L" SINi input "H" "L" IR bit in SiIC register "1" "0" SiTRF bit in S3456TRR register "1" "0" (1) (NOTE 2) D0 D1 D2 D3 D4 D5 D6 D7 i = 3 to 6 (5 and 6 are only in the 128-pin version.
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M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface 15.2.3 Functions for Setting SOUTi Initial Value If the SMi6 bit in the SiC register = 0 (external clock), the SOUTi pin output can be fixed high or low when not transferring (1). However, the last bit value of the former data is retained between data and data when transmitting the continuous data. Figure 15.41 shows the timing chart for setting an SOUTi initial value and how to set it. NOTE: 1.
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M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter 16. A/D Converter The MCU contains one A/D converter circuit based on 10-bit successive approximation method configured with a capacitive-coupling amplifier. The analog inputs share the pins with P10_0 to P10_7, P9_5, P9_6, _____________ P0_0 to P0_7, and P2_0 to P2_7. Similarly, ADTRG input shares the pin with P9_7. Therefore, when using these inputs, make sure the corresponding port direction bits are set to 0 (input mode).
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M16C/6N Group (M16C/6NK, M16C/6NM) 16.
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M16C/6N Group (M16C/6NK, M16C/6NM) 16.
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M16C/6N Group (M16C/6NK, M16C/6NM) 16.
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M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter 16.1 Mode Description 16.1.1 One-shot Mode In one-shot mode, analog voltage applied to a selected pin is converted to a digital code once. Table 16.2 lists the One-shot Mode Specifications. Figure 16.4 shows Registers ADCON0 and ADCON1 in One-shot Mode. Table 16.
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M16C/6N Group (M16C/6NK, M16C/6NM) 16.
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M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter 16.1.2 Repeat Mode In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table 16.3 lists the Repeat Mode Specifications. Figure 16.5 shows Registers ADCON0 and ADCON1 in Repeat Mode. Table 16.3 Repeat Mode Specifications Item Specification Function Bits CH2 to CH0 in the ADCON0 register, bits ADGSEL1 to ADGSEL0 in the ADCON2 register, and bits OPA1 to OPA0 in the ADCON1 register select a pin.
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M16C/6N Group (M16C/6NK, M16C/6NM) 16.
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M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter 16.1.3 Single Sweep Mode In single sweep mode, analog voltage that is applied to selected pins is converted one-by-one to a digital code. Table 16.4 lists the Single Sweep Mode Specifications. Figure 16.6 shows Registers ADCON0 and ADCON1 in Single Sweep Mode. Table 16.4 Single Sweep Mode Specifications Item Specification Function Bits SCAN1 to SCAN0 in the ADCON1 register and bits ADGSEL1 to ADGSEL0 in the ADCON2 register select pins.
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M16C/6N Group (M16C/6NK, M16C/6NM) 16.
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M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter 16.1.4 Repeat Sweep Mode 0 In repeat sweep mode 0, analog voltage applied to selected pins is repeatedly converted to a digital code. Table 16.5 lists the Repeat Sweep Mode 0 Specifications. Figure 16.7 shows Registers ADCON0 and ADCON1 in Repeat Sweep Mode 0. Table 16.5 Repeat Sweep Mode 0 Specifications Item Specification Function Bits SCAN1 to SCAN0 in the ADCON1 register and bits ADGSEL1 to ADGSEL0 in the ADCON2 register select pins.
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M16C/6N Group (M16C/6NK, M16C/6NM) 16.
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M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter 16.1.5 Repeat Sweep Mode 1 In repeat sweep mode 1, analog voltage selectively applied to all pins is repeatedly converted to a digital code. Table 16.6 lists the Repeat Sweep Mode 1 Specifications. Figure 16.8 shows Registers ADCON0 and ADCON1 in Repeat Sweep Mode 1. Table 16.
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M16C/6N Group (M16C/6NK, M16C/6NM) 16.
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M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter 16.2 Function 16.2.1 Resolution Select Function The desired resolution can be selected using the BITS bit in the ADCON1 register. If the BITS bit is set to 1 (10-bit conversion accuracy), the A/D conversion result is stored in the bits 0 to 9 in the ADi register (i = 0 to 7). If the BITS bit is set to 0 (8-bit conversion accuracy), the A/D conversion result is stored in the bits 0 to 7 in the ADi register. 16.2.
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M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter 16.2.5 Current Consumption Reducing Function When not using the A/D converter, its resistor ladder and reference voltage input pin (VREF) can be separated using the VCUT bit in the ADCON1 register. When separated, no current will flow from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip.
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M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter MCU Sensor equivalent circuit R0 VIN R (7.8 kΩ) Sampling time C (1.5 pF) VC Sample and hold enabled: 3 φAD Sample and hold disabled: 2 φAD Figure 16.10 Analog Input Pin and External Sensor Equivalent Circuit Rev.2.
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M16C/6N Group (M16C/6NK, M16C/6NM) 17. D/A Converter 17. D/A Converter This is an 8-bit, R-2R type D/A converter. These are two independent D/A converters. D/A conversion is performed by writing to the DAi register (i = 0, 1). To output the result of conversion, set the DAiE bit in the DACON register to 1 (output enabled). Before D/A conversion can be used, the corresponding port direction bit is set to 0 (input mode). Setting the DAiE bit to 1 removes a pull-up from the corresponding port.
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M16C/6N Group (M16C/6NK, M16C/6NM) 17. D/A Converter D/A Control Register (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset DACON 03DCh 00h Bit Symbol Bit Name Function DA0E D/A0 output enable bit 0 : Output disabled 1 : Output enabled DA1E D/A1 output enable bit 0 : Output disabled 1 : Output enabled (b7-b2) RW Nothing is assigned. If necessary, set to 0. When read, the content is 0. RW RW - NOTE: 1.
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M16C/6N Group (M16C/6NK, M16C/6NM) 18. CRC Calculation 18. CRC Calculation The Cyclic Redundancy Check (CRC) operation detects an error in data blocks. The MCU uses a generator polynomial of CRC-CCITT (X16 + X12 + X5 + 1) to generate CRC code. The CRC code consists of 16 bits which are generated for each data block in given length, separated in 8-bit unit. After the initial value is set in the CRCD register, the CRC code is set in that register each time one byte of data is written to the CRCIN register.
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M16C/6N Group (M16C/6NK, M16C/6NM) 18. CRC Calculation Setup procedure and CRC operation when generating CRC code "80C4h" CRC operation performed by the M16C CRC code: Remainder of a division in which the value written to the CRCIN register with its bit positions reversed is divided by the generator polynomial Generator polynomial: X6 +X12 +X5+1(1 0001 0000 0010 0001b) Setting procedure (1) Reverse the bit positions of the value "80C4h" by program in 1-byte unit.
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M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module 19. CAN Module The CAN (Controller Area Network) module for the M16C/6N Group (M16C/6NK, M16C/6NM) of MCUs is a communication controller implementing the CAN 2.0B protocol. The M16C/6N Group (M16C/6NK, M16C/6NM) contains two CAN modules which can transmit and receive messages in both standard (11-bit) ID and extended (29-bit) ID formats. Figure 19.1 shows the CAN Module Block Diagram. External CAN bus driver and receiver are required.
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M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module 19.1 CAN Module-Related Registers The CANi (i = 0, 1) module has the following registers. 19.1.1 CANi Message Box (i = 0, 1) A CAN module is equipped with 16 slots (16 bytes or 8 words each). Slots 14 and 15 can be used as Basic CAN. • Priority of the slots: The smaller the number of the slot, the higher the priority, in both transmission and reception. • A program can define whether a slot is defined as transmitter or receiver. 19.1.
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M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module 19.2 CANi Message Box (i = 0, 1) Table 19.1 shows the CANi Message Box Memory Mapping. It is possible to access to the message box in byte or word. Mapping of the message contents differs from byte access to word access. Byte access or word access can be selected by the MsgOrder bit in the CiCTLR register. Table 19.
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M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module Figures 19.2 and 19.3 show the Bit Mapping in Byte Access and Word Access. The content of each slot remains unchanged unless transmission or reception of a new message is performed.
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M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module 19.3 Acceptance Mask Registers Figures 19.4 and 19.5 show the Mask registers Bit Mapping (registers CiGMR (i = 0, 1), CiLMAR, and CiLMBR) in Byte Access and Word Access.
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M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module 19.4 CAN SFR Registers Figures 19.6 to 19.11 show the CAN SFR registers.
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M16C/6N Group (M16C/6NK, M16C/6NM) 19.
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M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module CANi Status Register (i = 0, 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol C0STR C1STR Address 0212h 0232h Bit Symbol Bit Name After Reset 00h 00h Function RW b3 b2 b1 b0 MBOX Active slot bits (1) 0 0 0 0 0 0. .. 1 1 1 1 0 0 : Slot 0 0 1 : Slot 1 1 0 : Slot 2 RO 1 0 : Slot 14 1 1 : Slot 15 TrmSucc Successful transmission flag (1) 0: No [successful] transmission 1: The CAN module has transmitted a message successfully.
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M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module CANi Slot Status Register (i = 0, 1) (b15) b7 (b8) b0 b7 b0 Symbol C0SSTR C1SSTR Address 0215h, 0214h 0235h, 0234h After Reset 0000h 0000h Setting Values RW 0: Reception slot The message has been read. Transmission slot Transmission is not completed. 1: Reception slot The message has not been read. Transmission slot Transmission is completed. RO Function Slot status bits Each bit corresponds to the slot with the same number.
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M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module CANi Configuration Register (i = 0, 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol C0CONR C1CONR Bit Symbol Address 021Ah 023Ah After Reset Undefined Undefined Bit Name Function RW b3 b2 b1 b0 0 0 0 0 : Divide-by-1 of fCAN 0 0 0 1 : Divide-by-2 of fCAN 0 0 1 0 : Divide-by-3 of fCAN .....
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M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module CANi Receive Error Count Register (i = 0, 1) b7 b0 Symbol C0RECR C1RECR Address 021Ch 023Ch After Reset 00h 00h Counter Value Function Reception error counting function The value is incremented or decremented according to the CAN module's error status. 00h to FFh (1) RW RO NOTE: 1. The value is undefined in bus off state.
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M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module 19.5 Operational Modes The CAN module has the following four operational modes. • CAN reset/Initialization mode • CAN operation mode • CAN sleep mode • CAN interface sleep mode Figure 19.12 shows the Transition between Operational Modes.
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M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module 19.5.2 CAN Operation Mode CAN operation mode is activated by setting the Reset bit in the CiCTLR register (i = 0, 1) to 0. If the Reset bit is set to 0, check that the State_Reset bit in the CiSTR register is set to 0.
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M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module 19.5.5 Bus Off State The bus off state is entered according to the fault confinement rules of the CAN specification. When returning to CAN operation mode from the bus off state, the module has the following two cases. In this time, the value of any CAN registers, except registers CiSTR, CiRECR, and CiTECR, does not change.
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M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module 19.6 CAN Module System Clock Configuration The M16C/6N Group (M16C/6NK, M16C/6NM) has a CAN module system clock select circuit. Configuration of the CAN module system clock can be done through manipulating the CCLKR register and the BRP bit in the CiCONR register (i = 0, 1). For the CCLKR register, refer to 8. Clock Generation Circuit. Figure 19.14 shows the CAN Module System Clock Generation Circuit Block Diagram.
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M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module 19.8 Bit-rate Bit-rate depends on f1, the division value of the CAN module system clock, the division value of the baud rate prescaler, and the number of Tq of one bit. Table 19.2 shows the Examples of Bit-rate. Table 19.2 Examples of Bit-rate Bit-rate 24 MHz (2) 1 Mbps 12 Tq (1) 500 kbps 8 Tq (3) 12 Tq (2) 24 Tq (1) 125 kbps 8 Tq (12) 12 Tq (8) 16 Tq (6) 24 Tq (4) 83.3 kbps 8 Tq (18) 12 Tq (12) 16 Tq (9) 24 Tq (6) 33.
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M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module 19.9 Acceptance Filtering Function and Masking Function These functions serve the users to select and receive a facultative message. Registers CiGMR (i = 0, 1), CiLMAR, and CiLMBR can perform masking to the standard ID and the extended ID of 29 bits. The CiGMR register corresponds to slots 0 to 13, the CiLMAR register corresponds to slot 14, and the CiLMBR register corresponds to slot 15.
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M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module 19.10 Acceptance Filter Support Unit (ASU) The acceptance filter support unit has a function to judge valid/invalid of a received ID through table search. The IDs to receive are registered in the data table; a received ID is stored in the CiAFS register ( i = 0, 1), and table search is performed with a decoded received ID. The acceptance filter support unit can be used for the IDs of the standard frame only.
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M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module 19.11 Basic CAN Mode When the BasicCAN bit in the CiCTLR register (i = 0, 1) is set to 1 (Basic CAN mode enabled), slots 14 and 15 correspond to Basic CAN mode. In normal operation mode, each slot can handle only one type message at a time, either a data frame or a remote frame by setting CiMCTLj regisrer (j = 0 to 15). However, in Basic CAN mode, slots 14 and 15 can receive both types of message at the same time.
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M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module 19.12 Return from Bus Off Function When the protocol controller enters bus off state, it is possible to make it forced return from bus off state by setting the RetBusOff bit in the CiCTLR register (i = 0, 1) to 1 (force return from bus off). At this time, the error state changes from bus off state to error active state.
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M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module 19.15 Reception and Transmission Table 19.3 lists the CAN Reception and Transmission Mode Configuration. Table 19.3 CAN Reception and Transmission Mode Configuration TrmReq RecReq Remote RspLock Communication Mode of Slot 0 0 Communication environment configuration mode: configure the communication mode of the slot. 0 1 0 0 Configured as a reception slot for a data frame. 1 0 1 0 Configured as a transmission slot for a remote frame.
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M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module 19.15.1 Reception Figure 19.20 shows the Timing of Receive Data Frame Sequence. Figure 19.20 shows the behavior of the module when receiving two consecutive CAN messages, that fit into the slot of the shown CiMCTLj register (i = 0, 1, j = 0 to 15) and leads to losing/overwriting of the first message.
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M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module 19.15.2 Transmission Figure 19.21 shows the Timing of Transmit Sequence. SOF ACK EOF IFS SOF (1) (4) TrmActive bit (1) (2) (3) SentData bit (3) CANi successful transmission interrupt (3) TrmState bit (1) (2) TrmSucc bit MBOX bit Transmission slot No. CiSTR register TrmReq bit CiMCTLj register CTX i = 0, 1 j = 0 to 15 Figure 19.
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M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module 19.16 CAN Interrupt The CAN module provides the following CAN interrupts.
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M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports 20. Programmable I/O Ports The programmable input/output ports (hereafter referred to simply as I/O ports) consist of 87 lines P0 to P10 in the 100-pin version and consist of 113 lines P0 to P14 in the 128-pin version. Each port can be set for input or output every line by using a direction register, and can also be chosen to be or not be pulled high_______ every 4 lines. P8_5 is an input-only port and does not have a pull-up resistor.
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M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports 20.1 PDi Register (100-pin Version: i = 0 to 10, 128-pin Version: i = 0 to 13) Figure 20.7 shows the PDi Register. This register selects whether the I/O port is to be used for input or output. The bits in this register correspond one for one to each port.
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M16C/6N Group (M16C/6NK, M16C/6NM) 20.
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M16C/6N Group (M16C/6NK, M16C/6NM) 20.
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M16C/6N Group (M16C/6NK, M16C/6NM) 20.
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M16C/6N Group (M16C/6NK, M16C/6NM) 20.
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M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Pull-up selection Direction register P8_7 Data bus Port latch (NOTE 1) fC Rf Pull-up selection Rd Direction register P8_6 1 Data bus Port latch Output (NOTE 1) NOTE: 1. Symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed VCC. Figure 20.5 I/O Ports (5) BYTE BYTE signal input (NOTE 1) CNVSS CNVSS signal input (NOTE 1) RESET RESET signal input (NOTE 1) NOTE: 1. Symbolizes a parasitic diode.
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M16C/6N Group (M16C/6NK, M16C/6NM) 20.
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M16C/6N Group (M16C/6NK, M16C/6NM) 20.
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M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Pull-up Control Register 0 (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR0 Bit Symbol Address 03FCh After Reset 00h Bit Name Function RW PU00 P0_0 to P0_3 pull-up PU01 P0_4 to P0_7 pull-up PU02 P1_0 to P1_3 pull-up RW PU03 P1_4 to P1_7 pull-up RW PU04 P2_0 to P2_3 pull-up RW PU05 P2_4 to P2_7 pull-up RW PU06 P3_0 to P3_3 pull-up RW PU07 P3_4 to P3_7 pull-up 0 : Not pulled high 1 : Pulled high (2) RW RW RW NOTES: 1.
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M16C/6N Group (M16C/6NK, M16C/6NM) 20.
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M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports Table 20.2 Unassigned Pin Handling in Single-chip Mode Pin Name Ports P0 to P7, P8_0 to P8_4, P8_6, P8_7, P9 to P14 (5) (4) XOUT _______ NMI(P8_5) AVCC AVSS, VREF, BYTE Connection After setting for input mode, connect every pin to VSS via a resistor (pull-down); or after setting for output mode, leave these pins open. (1) (2) (3) Open Connect via resistor to VCC (pull-up) Connect to VCC Connect to VSS NOTES: 1.
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M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports MCU MCU Port P0 to P14 (Input mode) (except for P8_5) (2) Port P6 to P14 (Input mode) (except for P8_5) (2) (Input mode) (Output mode) (Input mode) Open VCC VCC Port P4_5/CS1 to P4_7/CS3 NMI XOUT (Output mode) Open NMI BHE HLDA ALE XOUT VCC VCC Open BCLK (1) Open VCC AVCC HOLD BYTE RDY AVSS AVCC VREF AVSS VREF VSS VSS In single-chip mode In memory expansion mode or in microprocessor mode (3) NOTES: 1.
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M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory Version 21. Flash Memory Version Aside from the on-chip flash memory, the flash memory version MCU has the same functions as the masked ROM version. In the flash memory version, the flash memory can perform in four rewrite mode: CPU rewrite mode, standard serial I/O mode, parallel I/O mode, and CAN I/O mode. Table 21.1 lists the Flash Memory Version Specifications. See Tables 1.1 and 1.2 Functions and Specifications, for the items not listed in Table 21.
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M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory Version 21.1 Memory Map The flash memory contains the user ROM area and the boot ROM area. The user ROM area has space to store the MCU operating program in single-chip mode or memory expansion mode and a separate 4-Kbyte space as the block A. (Not available memory expansion mode in T/V-ver..) Figure 21.1 shows the Flash Memory Block Diagram.
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M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory Version 21.1.1 Boot Mode The MCU enters boot mode when a hardware reset occurs while an “H ” signal is applied to pins CNVSS and P5_0 and an “L ” signal is applied to the P5_5 pin. A program in the boot ROM area is executed. In boot mode, the FMR05 bit in the FMR0 register selects access to the boot ROM area or the user ROM area. The rewrite control program for standard serial I/O mode is stored in the boot ROM area before shipment.
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M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory Version ROM Code Protect Control Address (5) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ROMCP 1 1 1 1 1 1 Bit Symbol (b5-b0) Address 0FFFFFh Value when Shipped FFh (1) Bit Name Reserved bits Function Set to 1 RW RW b7 b6 ROMCP1 ROM code protect level 1 set bit (1) (2) (3) (4) 00: RW ROM code protection 01: active 10: 1 1 : ROM code protection inactive RW NOTES: 1.
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M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory Version 21.3 CPU Rewrite Mode In CPU rewrite mode, the user ROM area can be rewritten when the CPU executes software commands. The user ROM area can be rewritten with the MCU is mounted on a board without using a parallel, serial or CAN programmer. In CPU rewrite mode, only the user ROM area shown in Figure 21.1 can be rewritten. The boot ROM area cannot be rewritten. Program and the block erase command are executed only in the user ROM area.
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M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory Version 21.3.1 EW0 Mode The MCU enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to 1 (CPU rewrite mode enabled) and is ready to accept commands. EW0 mode is selected by setting the FMR11 bit in the FMR1 register to 0. To set the FMR01 bit to 1, set to 1 after first writing 0. The software commands control programming and erasing.
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M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory Version 21.3.3 Registers FMR0 and FMR1 Figure 21.4 shows Registers FMR0 and FMR1.
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M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory Version 21.3.3.1 FMR00 Bit This bit indicates the operating status of the flash memory. It is set to 0 while the program, block erase, erase all unlocked block, lock bit program, or read lock bit status command is being executed; otherwise, it is set to 1. 21.3.3.2 FMR01 Bit The MCU can accept commands when the FMR01 bit is set to 1 (CPU rewrite mode). Set the FMR05 bit to 1 (user ROM area access) as well if in boot mode. 21.3.3.
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M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory Version 21.3.3.7 FMR07 Bit This is a read-only bit indicating the status of an auto-erase operation. The FMR07 bit is set to 1 when an erase error occurs; otherwise, it is set to 0. For details, refer to 21.3.8 Full Status Check. 21.3.3.8 FMR11 Bit EW0 mode is entered by setting the FMR11 bit to 0 (EW0 mode). EW1 mode is entered by setting the FMR11 bit to 1 (EW1 mode). 21.3.3.
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M16C/6N Group (M16C/6NK, M16C/6NM) 21.
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M16C/6N Group (M16C/6NK, M16C/6NM) 21.
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M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory Version 21.3.4 Notes on CPU Rewrite Mode 21.3.4.1 Operating Speed Before entering CPU rewrite mode (EW0 or EW1 mode), set the CM11 bit in the CM1 register to 0 (main clock), select 10 MHz or less for CPU clock using the CM06 bit in the CM0 register and bits CM17 to CM16 in the CM1 register. Also, set the PM17 bit in the PM1 register to 1 (with wait state). 21.3.4.
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M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory Version 21.3.4.9 Writing Command and Data Write commands and data to even addresses in the user ROM area. 21.3.4.10 Wait Mode When entering wait mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) before executing the WAIT instruction. 21.3.4.
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M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory Version 21.3.5 Software Commands Software commands are described below. The command code and data must be read and written in 16-bit unit, to and from even addresses in the user ROM area. When writing command code, the high-order 8 bits (D15 to D8) are ignored. Table 21.4 lists the Software Commands. Table 21.
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M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory Version 21.3.5.4 Program Command (40h) The program command writes 2-byte data to the flash memory. By writing xx40h in the first bus cycle and data to the write address in the second bus cycle, an auto-program operation (data program and verify) will start. The address value specified in the first bus cycle must be the same even address as the write address specified in the second bus cycle.
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M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory Version 21.3.5.5 Block Erase Command The block erase command erases each block. By writing xx20h in the first bus cycle and xxD0h to the highest-order even address of a block in the second bus cycle, an auto-erase operation (erase and verify) will start in the specified block. The FMR00 bit in the FMR0 register indicates whether an auto-erase operation has been completed.
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M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory Version 21.3.5.6 Erase All Unlocked Block The erase all unlocked block command erases all blocks except the block A. By writing xxA7h in the first bus cycle and xxD0h in the second bus cycle, an auto-erase (erase and verify) operation will run continuously in all blocks except the block A. The FMR00 bit in the FMR0 register indicates whether an auto-erase operation has been completed.
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M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory Version 21.3.5.8 Read Lock Bit Status Command (71h) The read lock bit status command reads the lock bit state of a specified block. By writing xx71h in the first bus cycle and xxD0h to the highest-order even address of a block in the second bus cycle, the FMR16 bit in the FMR1 register stores information on whether or not the lock bit of a specified block is locked. Read the FMR16 bit after the FMR00 bit in the FMR0 register is set to 1 (ready).
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M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory Version 21.3.6 Data Protect Function Each block in the flash memory has a nonvolatile lock bit. The lock bit is enabled by setting the FMR02 bit in the FMR0 register to 0 (lock bit enabled). The lock bit allows each block to be individually protected (locked) against program and erase. This helps prevent data from being inadvertently written to or erased from the flash memory.
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M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory Version Table 21.
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M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory Version 21.3.8 Full Status Check If an error occurs when a program or erase operation is completed, the FMR06, FMR07 bits in the FMR0 register are set to 1, indicating a specific error. Therefore, execution results can be confirmed by checking these bits (full status check). Table 21.6 lists the Errors and FMR0 Register Status. Figure 21.12 shows a flow chart of the Full Status Check and Handling Procedure for Each Error. Table 21.
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M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory Version Full status check FMR06 =1 and FMR07=1? YES Command sequence error (1) Execute the clear status register command and set bits SR4 and SR5 to 0 (completed as expected). (2) Rewrite command and execute again. Erase error (1) Execute the clear status register command and set the SR5 bit to 0. (2) Execute the lock bit read status command.
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M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory Version 21.4 Standard Serial I/O Mode In standard serial I/O mode, the serial programmer supporting the M16C/6N Group (M16C/6NK, M16C/6NM) can be used to rewrite the flash memory user ROM area in the MCU mounted on a board. For more information about the serial programmer, contact your serial programmer manufacturer. Refer to the user's manual included with your serial programmer for instructions. Table 21.
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M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory Version Table 21.7 Pin Functions in Standard Serial I/O Mode Pin Name VCC1, VCC2, VSS Description I/O Apply the Flash Program, Erase Voltage to VCC1 pin and VCC2 to VCC2 pin. The VCC apply condition is that VCC2 = VCC1. Power supply input Apply 0 V to VSS pin. CNVSS I Connect to VCC1 pin. RESET Reset input I Reset input pin.
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21.
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21.
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M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory Version 21.4.2 Example of Circuit Application in Standard Serial I/O Mode Figures 21.15 and 21.16 show the Circuit Application in Standard Serial I/O Mode 1 and Mode 2. Refer to the user’s manual of your serial programmer to handle pins controlled by a serial programmer. Note that when using standard serial I/O mode 2, make sure a main clock input oscillation frequency is set to 5 MHz, 10 MHz, or 16 MHz.
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M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory Version 21.5 Parallel I/O Mode In parallel I/O mode, the user ROM area and the boot ROM area can be rewritten by a parallel programmer supporting the M16C/6N Group (M16C/6NK, M16C/6NM). Contact your parallel programmer manufacturer for more information on the parallel programmer. Refer to the user's manual included with your parallel programmer for instructions. 21.5.
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M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory Version 21.6 CAN I/O Mode In CAN I/O mode, the CAN programmer supporting the M16C/6N Group (M16C/6NK, M16C/6NM) can be used to rewrite the flash memory user ROM area in the MCU mounted on a board. For more information about the CAN programmer, contact your CAN programmer manufacturer. Refer to the user's manual included with your CAN programmer for instructions. Table 21.8 lists pin functions for CAN I/O mode. Figures 21.17 and 21.
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21.
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21.
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M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory Version 21.6.2 Example of Circuit Application in CAN I/O Mode Figure 21.19 shows the Circuit Application in CAN I/O Mode. Refer to the user’s manual of your CAN programmer to handle pins controlled by a CAN programmer. VCC1 VCC2 MCU P6_7/TXD1 P5_0(CE) P6_5/CLK1 P5_5(EPM) VCC1 CAN transceiver CAN_H CAN_L CAN_H P9_5/CRX0 CAN_L CNVSS P9_6/CTX0 VCC1 VCC1 RESET P8_5/NMI NOTES: 1.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) 22. Electrical Characteristics 22.1 Electrical Characteristics (Normal-ver.) Table 22.1 Absolute Maximum Ratings Symbol Parameter Condition Rated Value Unit VCC Supply voltage (VCC1 = VCC2) VCC = AVCC –0.3 to 6.5 V AVCC Analog supply voltage VCC = AVCC –0.3 to 6.5 V –0.3 to VCC+0.
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M16C/6N Group (M16C/6NK, M16C/6NM) Table 22.2 Recommended Operating Conditions (1) Symbol VCC AVCC VSS AVSS VIH VIL Parameter 22. Electric Characteristics (Normal-ver.) (1) Min. 3.0 Supply voltage (VCC1 = VCC2) Analog supply voltage Supply voltage Analog supply voltage HIGH input P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, 0.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) Table 22.3 Recommended Operating Conditions (2) Symbol f(XIN) (1) Parameter Min. Main clock input oscillation No wait Mask ROM version VCC = 3.0 to 5.5 V frequency (2) (3) (4) Standard Max. Typ.
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M16C/6N Group (M16C/6NK, M16C/6NM) Table 22.4 Electrical Characteristics (1) Symbol VOH HIGH output voltage 22. Electric Characteristics (Normal-ver.
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M16C/6N Group (M16C/6NK, M16C/6NM) Table 22.5 Electrical Characteristics (2) Symbol ICC 22. Electric Characteristics (Normal-ver.) (1) Parameter Power supply Measuring Condition In single-chip mode, Mask ROM current Min. f(BCLK) = 24 MHz, Standard Typ. Max. 21 37 Unit mA PLL operation, the output pins are (VCC = 3.0 to 5.5 V) open and other pins No division On-chip oscillation, No division 1 Flash memory f(BCLK) = 24 MHz, 23 are VSS.
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M16C/6N Group (M16C/6NK, M16C/6NM) Table 22.6 A/D Conversion Characteristics Symbol (1) Parameter – Resolution INL Integral 10 bits error 8 bits Absolute Measuring Condition Min. VREF = VCC VREF ANEX0, ANEX1 input, AN0 to AN7 input, Standard Typ. Max. 10 = VCC AN0_0 to AN0_7 input, AN2_0 to AN2_7 input = 5 V External operation amp connection mode nonlinearity – 22. Electric Characteristics (Normal-ver.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) Table 22.8 Flash Memory Version Electrical Characteristics Parameter Symbol (1) Min. (2) Standard Typ. Max. 25 200 µs Unit - Programming and erasure endurance - Word program time (VCC = 5.0 V) - Lock bit program time 25 200 µs - Block erase time 4-Kbyte block 0.3 4 s (VCC = 5.0 V) 8-Kbyte block 0.3 4 s 32-Kbyte block 0.5 4 s 64-Kbyte block 0.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) Timing Requirements VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified) =5V Table 22.11 External Clock Input (XIN Input) Symbol Parameter tC External clock input cycle time tw(H) External clock input HIGH pulse width tw(L) External clock input LOW pulse width tr External clock rise time tf External clock fall time Standard Min. Max. 62.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) Timing Requirements VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified) =5V Table 22.13 Timer A Input (Counter Input in Event Counter Mode) Parameter Symbol tc(TA) TAiIN input cycle time tw(TAH) TAiIN input HIGH pulse width tw(TAL) TAiIN input LOW pulse width Standard Min. Max. 100 40 40 Unit ns ns ns Table 22.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) Timing Requirements VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified) =5V Table 22.19 Timer B Input (Counter Input in Event Counter Mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) Standard Min. Max.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) Switching Characteristics VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified) =5V Table 22.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) Switching Characteristics VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified) =5V Table 22.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) Switching Characteristics VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified) =5V Table 22.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) VCC = 5 V Memory Expansion Mode and Microprocessor Mode (Effective for setting with wait) BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY–BCLK) th(BCLK–RDY) (Common to setting with wait and setting without wait) BCLK tsu(HOLD–BCLK) th(BCLK–HOLD) HOLD input HLDA output td(BCLK–HLDA) P0, P1, P2, P3, P4, P5_0 to P5_2 (1) td(BCLK–HLDA) Hi–Z NOTE: 1.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode (For setting with no wait) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) -4ns.min 25ns.max th(RD-AD) 0ns.min ALE td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min RD tac1(RD-DB) (0.5 ✕ tcyc-45)ns.max Hi-Z DBi tSU(DB-RD) 40ns.min th(RD-DB) 0ns.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode (For 1-wait setting and external area access) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(RD-AD) th(BCLK-ALE) 0ns.min -4ns.min 25ns.max ALE td(BCLK-RD) th(BCLK-RD) 0ns.min 25ns.max RD tac2(RD-DB) (1.5 ✕ tcyc-45)ns.max DBi Hi-Z th(RD-DB) tSU(DB-RD) 0ns.min 40ns.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode (For 2-wait setting and external area access) Read timing tcyc BCLK th(BCLK-CS) 4ns.min td(BCLK-CS) 25ns.max CSi th(BCLK-AD) 4ns.min td(BCLK-AD) 25ns.max ADi BHE td(BCLK-ALE) 25ns.max th(RD-AD) 0ns.min th(BCLK-ALE) -4ns.min ALE th(BCLK-RD) 0ns.min td(BCLK-RD) 25ns.max RD tac2(RD-DB) (2.5 ✕ tcyc-45)ns.max DBi Hi-Z tSU(DB-RD) 40ns.min th(RD-DB) 0ns.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) VCC = 5 V Memory Expansion Mode and Microprocessor Mode (For 3-wait setting and external area access) Read timing tcyc BCLK th(BCLK-CS) 4ns.min td(BCLK-CS) 25ns.max CSi th(BCLK-AD) 4ns.min td(BCLK-AD) 25ns.max ADi BHE td(BCLK-ALE) 25ns.max th(RD-AD) 0ns.min th(BCLK-ALE) -4ns.min ALE th(BCLK-RD) 0ns.min td(BCLK-RD) 25ns.max RD tac2(RD-DB) (3.5 ✕ tcyc-45)ns.max DBi Hi-Z tSU(DB-RD) th(RD-DB) 0ns.min 40ns.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) VCC = 5 V Memory Expansion Mode and Microprocessor Mode (For 1- or 2-wait setting, external area access and multiplexed bus selection) Read timing BCLK td(BCLK-CS) th(RD-CS) (0.5 ✕ tcyc-10)ns.min tcyc 25ns.max th(BCLK-CS) 4ns.min CSi td(AD-ALE) (0.5 ✕ tcyc-25)ns.min ADi /DBi th(ALE-AD) (0.5 ✕ tcyc-15)ns.min Address 8ns.max Address Data input tdZ(RD-AD) tac3(RD-DB) (1.5 ✕ tcyc-45)ns.max tSU(DB-RD) th(RD-DB) 0ns.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) VCC = 5 V Memory Expansion Mode and Microprocessor Mode (For 3-wait setting, external area access and multiplexed bus selection) Read timing tcyc BCLK th(RD-CS) (0.5 ✕ tcyc-10)ns.min td(BCLK-CS) th(BCLK-CS) 4ns.min 25ns.max CSi td(AD-ALE) (0.5 ✕ tcyc-25)ns.min ADi /DBi th(ALE-AD) (0.5 ✕ tcyc-15)ns.min Address td(BCLK-AD) td(AD-RD) 25ns.max ADi BHE Data input tdZ(RD-AD) 8ns.max tac3(RD-DB) (2.5 ✕ tcyc-45)ns.
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M16C/6N Group (M16C/6NK, M16C/6NM) Table 22.28 Electrical Characteristics 22. Electric Characteristics (Normal-ver.) (1) VCC = 3.3 V Standard Parameter Measuring Condition Unit Symbol Min. Typ. Max. VCC P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH = –1 mA V VOH HIGH output VCC-0.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) Timing Requirements VCC (Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified) = 3.3 V Table 22.29 External Clock Input (XIN Input) Symbol Parameter tC External clock input cycle time tw(H) External clock input HIGH pulse width tw(L) External clock input LOW pulse width tr External clock rise time tf External clock fall time Standard Min. Max. 62.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) Timing Requirements VCC (Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified) = 3.3 V Table 22.31 Timer A Input (Counter Input in Event Counter Mode) Parameter Symbol tc(TA) TAiIN input cycle time tw(TAH) TAiIN input HIGH pulse width tw(TAL) TAiIN input LOW pulse width Standard Min. Max. 150 60 60 Unit ns ns ns Table 22.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) Timing Requirements VCC (Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified) = 3.3 V Table 22.37 Timer B Input (Counter Input in Event Counter Mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) Standard Min. Max.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) Switching Characteristics VCC (Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified) = 3.3 V Table 22.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) Switching Characteristics VCC (Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified) = 3.3 V Table 22.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) Switching Characteristics VCC (Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified) = 3.3 V Table 22.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) VCC = 3.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode VCC = 3.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode (For setting with no wait) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 30ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 30ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) -4ns.min 30ns.max th(RD-AD) 0ns.min ALE td(BCLK-RD) 30ns.max th(BCLK-RD) 0ns.min RD tac1(RD-DB) (0.5 ✕ tcyc-60)ns.max Hi-Z DBi tSU(DB-RD) 50ns.min th(RD-DB) 0ns.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode (For 1-wait setting and external area access) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 30ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 30ns.max 4ns.min ADi BHE td(BCLK-ALE) th(RD-AD) th(BCLK-ALE) 0ns.min -4ns.min 30ns.max ALE td(BCLK-RD) th(BCLK-RD) 0ns.min 30ns.max RD tac2(RD-DB) (1.5 ✕ tcyc-60)ns.max DBi Hi-Z th(RD-DB) tSU(DB-RD) 0ns.min 50ns.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode (For 2-wait setting and external area access) Read timing tcyc BCLK th(BCLK-CS) 4ns.min td(BCLK-CS) 30ns.max CSi th(BCLK-AD) 4ns.min td(BCLK-AD) 30ns.max ADi BHE td(BCLK-ALE) 30ns.max th(RD-AD) 0ns.min th(BCLK-ALE) -4ns.min ALE th(BCLK-RD) 0ns.min td(BCLK-RD) 30ns.max RD tac2(RD-DB) (2.5 ✕ tcyc-60)ns.max DBi Hi-Z tSU(DB-RD) 50ns.min th(RD-DB) 0ns.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) VCC = 3.3 V Memory Expansion Mode and Microprocessor Mode (For 3-wait setting and external area access) Read timing tcyc BCLK th(BCLK-CS) 4ns.min td(BCLK-CS) 30ns.max CSi th(BCLK-AD) 4ns.min td(BCLK-AD) 30ns.max ADi BHE td(BCLK-ALE) 30ns.max th(RD-AD) 0ns.min th(BCLK-ALE) -4ns.min ALE th(BCLK-RD) 0ns.min td(BCLK-RD) 30ns.max RD tac2(RD-DB) (3.5 ✕ tcyc-60)ns.max DBi Hi-Z tSU(DB-RD) th(RD-DB) 0ns.min 50ns.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) VCC = 3.3 V Memory Expansion Mode and Microprocessor Mode (For 2-wait setting, external area access and multiplexed bus selection) Read timing BCLK td(BCLK-CS) th(RD-CS) (0.5 ✕ tcyc-10)ns.min tcyc 40ns.max th(BCLK-CS) 4ns.min CSi td(AD-ALE) (0.5 ✕ tcyc-40)ns.min ADi /DBi Address th(ALE-AD) (0.5 ✕ tcyc-15)ns.min 8ns.max Address Data input tdZ(RD-AD) tac3(RD-DB) (1.5 ✕ tcyc-60)ns.max tSU(DB-RD) th(RD-DB) 0ns.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode VCC = 3.3 V (For 3-wait setting, external area access and multiplexed bus selection) Read timing tcyc BCLK th(RD-CS) (0.5 ✕ tcyc-10)ns.min td(BCLK-CS) th(BCLK-CS) 6ns.min 40ns.max CSi td(AD-ALE) (0.5 ✕ tcyc-40)ns.min ADi /DBi th(ALE-AD) (0.5 ✕ tcyc-15)ns.min Address td(BCLK-AD) td(AD-RD) 40ns.max ADi BHE Data input tdZ(RD-AD) 8ns.max tac3(RD-DB) (2.5 ✕ tcyc-60)ns.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (T/V-ver.) 22.2 Electrical Characteristics (T/V-ver.) Table 22.46 Absolute Maximum Ratings Symbol Parameter Condition Rated Value Unit VCC Supply voltage (VCC1 = VCC2) VCC = AVCC –0.3 to 6.5 V AVCC Analog supply voltage VCC = AVCC –0.3 to 6.5 V –0.3 to VCC+0.3 V –0.3 to 6.5 V –0.3 to VCC+0.3 V –0.3 to 6.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (T/V-ver.) Table 22.47 Recommended Operating Conditions (1) Symbol (1) Parameter VCC Supply voltage (VCC1 = VCC2) AVCC Analog supply voltage VSS Supply voltage AVSS Analog supply voltage VIH HIGH input voltage Min. 4.2 Standard Max. Typ. 5.0 VCC Unit 5.5 0 0 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, 0.8 VCC P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, V V V V VCC V 6.5 0.2 VCC V –10.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (T/V-ver.) Table 22.48 Recommended Operating Conditions (2) Symbol f(XIN) (1) Parameter Main clock input oscillation No wait Flash memory frequency (2) (3) (4) Min. VCC = 4.2 to 5.5 V Standard Max. Typ.
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M16C/6N Group (M16C/6NK, M16C/6NM) Table 22.49 Electrical Characteristics (1) (1) Parameter Symbol VOH 22. Electric Characteristics (T/V-ver.
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M16C/6N Group (M16C/6NK, M16C/6NM) Table 22.50 Electrical Characteristics (2) Symbol ICC 22. Electric Characteristics (T/V-ver.) (1) Parameter Power supply current Measuring Condition Min. Output pins are open Flash memory f(BCLK) = 20 MHz, PLL operation, and other pins are VSS. (VCC = 4.2 to 5.5 V) Standard Typ. Max. 36 21 Unit mA No division On-chip oscillation, No division 1.8 mA Flash memory f(BCLK) = 10 MHz, 15 mA 25 mA 25 µA 420 µA 50 µA 8.5 µA 3.
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M16C/6N Group (M16C/6NK, M16C/6NM) Table 22.51 A/D Conversion Characteristics Symbol Parameter – Resolution INL integral 10 bits erro 8 bits Absolute (1) Measuring Condition Min. VREF = VCC VREF ANEX0, ANEX1 input, AN0 to AN7 input, Standard Typ. Max. 10 = VCC AN0_0 to AN0_7 input, AN2_0 to AN2_7 input = 5 V External operation amp connection mode nonlinearity – 22. Electric Characteristics (T/V-ver.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (T/V-ver.) Table 22.53 Flash Memory Version Electrical Characteristics Parameter Symbol (1) Min. (2) Standard Typ. Max. 25 200 µs Unit - Programming and erasure endurance - Word program time (VCC = 5.0 V) - Lock bit program time 25 200 µs - Block erase time 4-Kbyte block 0.3 4 s (VCC = 5.0 V) 8-Kbyte block 0.3 4 s 32-Kbyte block 0.5 4 s 64-Kbyte block 0.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (T/V-ver.) Timing Requirements VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified) =5V Table 22.56 External Clock Input (XIN Input) Symbol Parameter Standard Min. Max. 62.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (T/V-ver.) Timing Requirements VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified) =5V Table 22.63 Timer B Input (Counter Input in Event Counter Mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) Standard Min. Max.
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M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (T/V-ver.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23. Usage Notes 23.1 SFRs There are the SFRs with write-only bits which can only be written to. Set these registers with undefined values. When establishing the next value by altering the present value, write the present value to the RAM as well as to the register. Transfer the next value to the register after making changes in the RAM. Table 23.1 lists Registers with Write-only Bits. Table 23.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23.2 External Bus (Normal-ver. only) When resetting CNVSS pin with "H" input, contents of internal ROM cannot be read out. Rev.2.10 Apr 14, 2006 REJ09B0124-0210 page 339 of 378 23.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.3 External Clock Do not stop the external clock when it is connected to the XIN pin and the main clock is selected as the CPU clock. Rev.2.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.4 PLL Frequency Synthesizer Stabilize supply voltage so that the standard of the power supply ripple is met. (Refer to 22. Electrical characteristics.) Rev.2.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.5 Power Control ____________ • When exiting stop mode by hardware reset, set RESET pin to “L” until a main clock oscillation is stabilized. • Set the MR0 bit in the TAiMR register (i = 0 to 4) to 0 (pulse is not output) to use the timer A to exit stop mode. • In the main clock oscillation or low power dissipation mode, set the CM02 bit in the CM0 register to 0 (do not stop peripheral function clock in wait mode) before shifting to stop mode.
PAGE 367
M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes • When entering medium-speed mode after transferring to stop mode from low-speed mode and low power dissipation mode, write the MOV instruction (MOV.W #IMM16, abs16) as described below. When entering stop mode and exiting from stop mode, DMA transfer must be disabled. Change the src value (marked as “#2118”) depending on your usage condition. MOV.W #2118H,CM0 JMP.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.6 Oscillation Stop, Re-oscillation Detection Function If the following conditions are all met, the following restriction occur in operation of oscillation stop, re-oscillation stop detection interrupt.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.7 Protection Set the PRC2 bit in the PRCR register to 1 (write enabled) and then write to given address, and the PRC2 bit will be set to 0 (write protected). The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2 bit to 1. Make sure no interrupts or no DMA transfers will occur between the instruction in which the PRC2 bit is set to 1 and the next instruction. Rev.2.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.8 Interrupts 23.8.1 Reading Address 00000h Do not read the address 00000h in a program. When a maskable interrupt request is accepted, the CPU reads interrupt information (interrupt number and interrupt request priority level) from the address 00000h during the interrupt sequence. At this time, the IR bit for the accepted interrupt is set to 0.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.8.4 Changing Interrupt Source If the interrupt source is changed, the IR bit in the interrupt control register for the changed interrupt may inadvertently be set to 1 (interrupt requested). If you changed the interrupt source for an interrupt that needs to be used, be sure to set the IR bit for that interrupt to 0 (interrupt not requested).
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.8.6 Rewrite Interrupt Control Register (a) The interrupt control register for any interrupt should be modified in places where no requests for that interrupt may be generated. Otherwise, disable the interrupt before rewriting the interrupt control register. (b) To rewrite the interrupt control register for any interrupt after disabling that interrupt, care must be taken when selecting the instructions.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.9 DMAC 23.9.1 Write to DMAE Bit in DMiCON Register (i = 0, 1) When both of the conditions below are met, follow the steps below. Conditions • The DMAE bit is set to 1 again while it remains set (DMAi is in an active state). • A DMA request may occur simultaneously when the DMAE bit is being written. Step 1: Write 1 to the DMAE bit and DMAS bit in the DMiCON register simultaneously (1).
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.10 Timers 23.10.1 Timer A 23.10.1.1 Timer A (Timer Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to 1 (count starts). Always make sure the TAiMR register is modified while the TAiS bit remains 0 (count stops) regardless whether after reset or not.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.10.1.2 Timer A (Event Counter Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the UDF register, bits TAZIE, TA0TGL, and TA0TGH in the ONSF register, and the TRGSR register before setting the TAiS bit in the TABSR register to 1 (count starts).
PAGE 376
M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.10.1.3 Timer A (One-shot Timer Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, bits TA0TGL and TA0TGH in the ONSF register, and the TRGSR register before setting the TAiS bit in the TABSR register to 1 (count starts).
PAGE 377
M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.10.1.4 Timer A (Pulse Width Modulation Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, bits TA0TGL and TA0TGH in the ONSF register, and the TRGSR register before setting the TAiS bit in the TABSR register to 1 (count starts).
PAGE 378
M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.10.2 Timer B 23.10.2.1 Timer B (Timer Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i = 0 to 5) register and TBi register before setting the TBiS bit (1) in the TABSR or the TBSR register to 1 (count starts). Always make sure the TBiMR register is modified while the TBiS bit remains 0 (count stops) regardless whether after reset or not. NOTE: 1.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.10.2.3 Timer B (Pulse Period/pulse Width Measurement Mode) The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR (i = 0 to 5) register before setting the TBiS bit in the TABSR or TBSR register to 1 (count starts). Always make sure the TBiMR register is modified while the TBiS bit remains 0 (count stops) regardless whether after reset or not.
PAGE 380
M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.11 Thee-Phase Motor Control Timer Function If there is a possibility that you may write data to TAi-1 register (i = 1, 2, 4) near Timer B2 overflow, read the value of TB2 register, verify that there is sufficient time until Timer B2 overflows, before doing an immediate write to TAi-1 register. In order to shorten the period from reading TB2 register to writing data to TAi-1 register, ensure that no interrupt will be processed during this period.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.12 Serial Interface 23.12.1 Clock Synchronous Serial I/O Mode 23.12.1.1 Transmission/reception _______ ________ With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes to “L” when the data-receivable status becomes ready, which informs the transmission side that the reception ________ ________ has become ready. The output level of the RTSi pin goes to “H” when reception starts.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.12.2 Special Modes 23.12.2.1 Special Mode 1 (I2C Mode) When generating start, stop and restart conditions, set the STSPSEL bit in the UiSMR4 register to 0 (start and stop conditions not output) and wait for more than half cycle of the transfer clock before setting each condition generate bit (bits STAREQ, RSTAREQ, and STPREQ) from 0 (clear) to 1 (start). 23.12.2.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.12.3 SI/Oi (i = 3 to 6) (1) The SOUTi default value which is set to the SOUTi pin by the SMi7 in the SiC register bit approximately 10 ns may be output when changing the SMi3 bit in the SiC register from 0 (I/O port) to 1 (SOUTi output and CLKi function) while the SMi2 bit in the SiC register to 0 (SOUTi output) and the SMi6 bit is set to 1 (internal clock). And then the SOUTi pin is held high-impedance.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.13 A/D Converter Set the ADCON0 (except bit 6), registers ADCON1 and ADCON2 when A/D conversion is stopped (before a trigger occurs). After stopping A/D conversion, the VCUT bit in the ADCON1 register is changed from 1 (VREF connected) to 0 (VREF not connected), When the VCUT bit is changed from 0 to 1, start A/D conversion after passing 1 µs or longer.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes If the CPU reads the ADi register (i = 0, 1) at the same time the conversion result is stored in the ADi register after completion of A/D conversion, an incorrect value may be stored in the ADi register. This problem occurs when a divide-by-n clock derived from the main clock or a sub clock is selected for CPU clock. • When operating in one-shot or single-sweep mode Check to see that A/D conversion is completed before reading the target ADi register.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.14 CAN Module 23.14.1 Reading CiSTR Register (i = 0, 1) The CAN module on the M16C/6N Group (M16C/6NK, M16C/6NM) updates the status of the CiSTR register in a certain period. When the CPU and the CAN module access to the CiSTR register at the same time, the CPU has the access priority; the access from the CAN module is disabled.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes fCAN CPU read signal Updating period of CAN module CPU reset signal ✕ CiSTR register b8: State_Reset bit 0: CAN operation mode 1: CAN reset/initialization mode ✕ ✕ ✕ ✕ ✕: When the CAN module’s State_Reset bit updating period matches the CPU’s read period, it does not enter reset mode, for the CPU read has the higher priority. i = 0, 1 Figure 23.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.14.2 Performing CAN Configuration If the Reset bit in the CiCTLR register (i = 0, 1) is changed from 0 (operation mode) to 1 (reset/initialization mode) in order to place the CAN module from CAN operation mode into CAN reset/initialization mode, always be sure to check that the State_Reset bit in the CiSTR register is set to 1 (reset mode).
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.14.3 Suggestions to Reduce Power Consumption When not performing CAN communication, the operation mode of CAN transceiver should be set to “standby mode” or “sleep mode”. When performing CAN communication, the power consumption in CAN transceiver in not performing CAN communication can be substantially reduced by controlling the operation mode pins of CAN transceiver. Tables 23.3 and 23.4 show the Recommended Pin Connections. Table 23.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.14.4 CAN Transceiver in Boot Mode When programming the flash memory in boot mode via CAN bus, the operation mode of CAN transceiver should be set to “high-speed mode” or “normal operation mode”. If the operation mode is controlled by the microcomputer, CAN transceiver must be set the operation mode to “high-speed mode” or “normal operation mode” before programming the flash memory by changing the switch etc. Tables 23.5 and 23.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.15 Programmable I/O Ports_______ If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase _______ output forcible cutoff by input on NMI pin enabled), pins P7_2 to P7_5, P8_0 and P8_1 go to a high-impedance state. Setting the SM32 bit in the S3C register to 1 causes the P9_2 pin to go to a high-impedance state.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.16 Dedicated Input Pin When dedicated input pin voltage is larger than VCC pin voltage, latch up occurs. When different power supplied to the system, and input voltage of unused dedicated input pin is larger than voltage of VCC pin, connect dedicated input pin to VCC via resistor (approximately 1 kΩ). Figure 23.8 shows the Circuit Connection. This note is also applicable when VINPUT exceeds VCC during power-up.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.17 Electrical Characteristic Differences between Mask ROM and Flash Memory Version MCUs Flash memory version and mask ROM version may have different characteristics, operating margin, noise tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout pattern, etc. When switching to the mask ROM version, conduct equivalent tests as system evaluation tests conducted in the flash memory version.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23.18 Mask ROM Version (Normal-ver. only) When using the masked ROM version, write nothing to internal ROM area. Rev.2.10 Apr 14, 2006 REJ09B0124-0210 page 370 of 378 23.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.19 Flash Memory Version 23.19.1 Functions to Prevent Flash Memory from Rewriting ID codes are stored in addresses 0FFFDFh, 0FFFE3h, 0FFFEBh, 0FFFEFh, 0FFFF3h, 0FFFF7h, and 0FFFFBh. If wrong data are written to theses addresses, the flash memory cannot be read or written in standard serial I/O mode and CAN I/O mode. The ROMCP register is mapped in address 0FFFFFh.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.19.9 Prohibited Instructions The following instructions cannot be used in EW0 mode because the CPU tries to read data in flash memory: the UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction 23.19.10 Interrupts EW0 Mode To use interrupts having vectors in a relocatable vector table, the vectors must be relocated to the RAM area.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.20 Flash Memory Programming Using Boot Program When programming the internal flash memory using boot program, be careful about the pins state and connection as follows. 23.20.1 Programming Using Serial I/O Mode CTX0 pin : This pin automatically outputs “H” level. CRX0 pin : Connect to CAN transceiver or connect via resister to VCC (pull-up) Figure 23.9 shows the Pin Connection for Programming Using Serial I/O Mode.
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M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes 23.21 Noise Connect a bypass capacitor (approximately 0.1 µF) across pins VCC1 and VSS, and pins VCC2 and VSS using the shortest and thicker possible wiring. Figure 23.11 shows the Bypass Capacitor Connection. Bypass capacitor Connecting pattern VSS Connecting pattern VCC2 M16C/6N Group (M16C/6NK, M16C/6NM) VSS Connecting pattern VCC1 Connecting pattern Bypass capacitor Figure 23.11 Bypass Capacitor Connection Rev.2.
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M16C/6N Group (M16C/6NK, M16C/6NM) Appendix 1. Package Dimensions Appendix 1. Package Dimensions JEITA Package Code P-LQFP100-14x14-0.50 RENESAS Code PLQP0100KB-A Previous Code 100P6Q-A / FP-100U / FP-100UV MASS[Typ.] 0.6g HD *1 D 51 75 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
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M16C/6N Group (M16C/6NK, M16C/6NM) Memo Rev.2.10 Apr 14, 2006 REJ09B0124-0210 page 376 of 378 Appendix 1.
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M16C/6N Group (M16C/6NK, M16C/6NM) Register Index Register Index A DM0CON, DM1CON ..................... 106 S3IC, S4IC ...................................... 87 AD0 to AD7 ................................... 205 DM0IC, DM1IC ................................ 86 DM0SL .......................................... 105 S3TRR to S6TRR .......................... 137 S5IC, S6IC ...................................... 86 DM1SL .......................................... 106 DTT ..................................
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M16C/6N Group (M16C/6NK, M16C/6NM) U U0BCNIC to U2BCNIC ..................... 86 U0BRG to U2BRG ........................ 153 U0C0 to U2C0 ............................... 154 U0C1 to U2C1 ............................... 155 U0MR to U2MR ............................. 154 U0RB to U2RB .............................. 153 U0SMR to U2SMR ........................ 156 U0SMR2 to U2SMR2 .................... 157 U0SMR3 to U2SMR3 .................... 157 U0SMR4 to U2SMR4 .................... 158 U0TB to U2TB ..........
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REVISION HISTORY Rev. Date 1.00 Sep. 30, 2004 1.01 Nov. 01, 2004 Description Page Summary – – First edition issued Revised edition issued * Revised parts and revised contents are as follows (except for expressional change). Table 1.2 Performance Outline of M16C/6N Group (128-pin Version: M16C/6NM) • Interrupt: Internal interrupt source is revised from “32 sources” to “34 sources”. Table 21.2 Recommended Operating Conditions (1) • IOH(peak): Unit is revised from “V” to “mA”. Table 21.
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REVISION HISTORY Rev. Date 1.10 Jul. 01, 2005 Description Page Summary 212 Figure 18.11 C0RECR, C1RECR Registers, C0TECR, C1TECR Registers, C0TSR, C1TSR Registers, and C0AFS, C1AFS Registers • C0RECR, C1RECR Registers: NOTE 2 is deleted. • C0TECR, C1TECR Registers: NOTE 1 is deleted. • C0TSR, C1TSR Registers: NOTE 1 is deleted. 18.15.1 Reception (1): “(refer to 18.15.2 Transmission)” is deleted. Figure 19.1 I/O Ports (1): “P7_0” in 4th figure is deleted. Figure 19.
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REVISION HISTORY Rev. Date 2.00 Nov. 28, 2005 M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Description Page Summary 37 5.2 Software Reset, 5.3 Watchdog Timer Reset, 5.4 Oscillation Stop Detection Reset: Last sentence (Processor mode remains ...) is added to each section. 5.5 Internal Space is added. 6.1 Types Processor Mode is added. Table 6.1 Features of Processor Modes is added. 6.2 Setting Processor Modes is added. Table 6.2 Processor Mode After Hardware Reset and Table 6.
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REVISION HISTORY Rev. Date 2.00 Nov. 28, 2005 M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Description Page Summary 108 12.1.3 Effect of Software Wait: 3rd to 9th lines is moved from next section of 12.1.2. ________ 12.1.4 Effect of RDY Signal is added. Table 12.2 DMA Transfer Cycles is revised. Table 12.3 Coefficient j, k is revised. 12.5 Channel Priority and DMA Transfer Timing: Last sentence (Refer to ...) is added. Figure 13.
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REVISION HISTORY Rev. Date 2.00 Nov. 28, 2005 M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Description Page Summary 258 Table 20.3 Unassigned Pin Handling in Memory Expansion Mode and Microprocessor Mode (Normal-ver. only) is added. Figure 20.12 Unassigned Pins Handling • Figure of memory expansion mode or microprocessor mode is added. • NOTES 1 and 3 are added. Table 21.2 Flash Memory Rewrite Modes Overview • Operation Mode of CPU Rewrite Mode is revised. • NOTE 2 is revised.
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REVISION HISTORY Rev. Date 2.00 Nov. 28, 2005 M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Description Page Summary 291 Figure 21.19 Circuit Application in CAN I/O Mode: “VCC1” and “VCC2” are added. 293 Table 22.2 Recommended Operating Conditions (1) ________ is partly revised. __________ 297 Table 22.4 Electrical Characteristics (1): HOLD and RDY are added to VT+ - VT-. 299 Table 22.12 Memory Expansion Mode and Microprocessor Mode is added.
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REVISION HISTORY Rev. Date M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Description Page Summary 2.10 Apr.14, 2006 150, 151 Figures 15.1 to 15.3 are revised. 153 154 159 162 167 170 171 175 177 184 191 193 195 197 199 200 201 220 229 233 234 235 238 258 295 313 331 342 343 Figure 15.5 Registers U0RB to U2RB (middle): NOTE 3 is added. Figure 15.6 Registers U0C0 to U2C0 (lower): NOTE 6 is added. Table 15.
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REVISION HISTORY Rev. Date 2.10 Apr.14, 2006 M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Description Page 360 Summary 23.13 A/D Converter • 1st item: “After stopping ...” is added.
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M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Publication Data : Rev.1.00 Sep 30, 2004 Rev.2.10 Apr 14, 2006 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
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M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual REJ09B0124-0210